Signal aware energy efficient approach for low power full adder design with adiabatic logic
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TECHNICAL PAPER
Signal aware energy efficient approach for low power full adder design with adiabatic logic Dinesh Kumar1
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Manoj Kumar1
Received: 26 August 2019 / Accepted: 10 October 2020 Ó Springer-Verlag GmbH Germany, part of Springer Nature 2020
Abstract Prolonged battery life is the major concern for modern low power electronic devices. Concentrating on this issue, in this paper a new structure of full adder has been proposed. Based on this architecture four new designs of low power full adder have been proposed. Two designs of proposed full adder i.e., A1 and A3 consist of four and three transistors based X-NOR gate respectively. Functionality of these two designs also verified with improved performance by employing diode free adiabatic logic (DFAL) in proposed adders, A2, and A4. Signal aware power efficient inverters have been used for proposed designs. Proposed adder designs are fast and consume less power as compared to the existing adders reported in literature. The proposed designs show a power delay product (PDP) of 0.041 fJ, 0.016 fJ, 0.054 fJ, and 0.047 fJ for adder A1, A2, A3 and, A4 respectively as compared to best reported double pass transistor full adder with 0.061 fJ. The proposed designs also perform well at stringent temperature, capacitance and, frequency conditions. These designs show satisfactory performance at low voltages whereas; the use of adiabatic logic makes these designs energy efficient for low power applications.
1 Introduction In rapidly developing low power electronics industry the demand for portable electronic devices is increasing day by day. These devices consist of high speed data processors, which are responsible for the arithmetical operation of these devices. Complementary metal oxide semiconductor (CMOS) based circuits are the backbone of these processors. These processors perform complex computations for various applications such as: for large-scale industrial automation, image processing, space and modern warfare industry. Miniaturized devices like personal digital assistants (PDA), mobile phones, biomedical implantable devices consist of digital signal processor (DSP) units (Tonfat and Reis 2012). These units are used to execute the dedicated algorithms like convolution and filtering (Chang et al. 2004), which primarily depends on the efficient implementation of generic arithmetic logic and floating & Dinesh Kumar [email protected] Manoj Kumar [email protected] 1
USIC&T, Guru Gobind Singh Indraprastha University, Sec16C, Dwarka, New Delhi 110078, India
point units. These logic units composed of the multiplier and high speed adders. The high speed adders play a vital role in these processors and responsible for system performance which deals with complex computations. Therefore to prolong the battery life of the system by reducing the power dissipation, researchers need to search novel and hybrid techniques for the implementation of adders. As the scaling (reduction in feature size) is improved, limitati
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