Current Status of the Quality of 4H-SiC Substrates and Epilayers for Power Device Applications
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Current Status of the Quality of 4H-SiC Substrates and Epilayers for Power Device Applications M. Dudley1, H. Wang1, Jianqiu Guo1, Yu Yang1, Balaji Raghothamachar1 Department of Materials Science and Engineering, Stony Brook University, Stony Brook NY 11794-2275, U.S.A. 1
J. Zhang2, B. Thomas2, G. Chung2, E. K. Sanchez2, D. Hansen2, and S. G. Mueller2 2 Dow Corning Compound Semiconductor Solutions, Midland, Michigan, USA 48686 ABSTRACT Interfacial dislocations (IDs) and half-loop arrays (HLAs) present in the epilayers of 4HSiC crystal are known to have a deleterious effect on device performance. Synchrotron X-ray Topography studies carried out on n-type 4H-SiC offcut wafers before and after epitaxial growth show that in many cases BPD segments in the substrate are responsible for creating IDs and HLAs during CVD growth. This paper reviews the behaviors of BPDs in the substrate during the epitaxial growth in different cases: (1) screw-oriented BPD segments intersecting the surface replicate directly through the interface during the epitaxial growth and take part in stress relaxation process by creating IDs and HLAs (Matthews-Blakeslee model [1] ); (2) non-screw oriented BPD half loop intersecting the surface glides towards and replicates through the interface, while the intersection points convert to threading edge dislocations (TEDs) and pin the half loop, leaving straight screw segments in the epilayer and then create IDs and HLAs; (3) edge oriented short BPD segments well below the surface get dragged towards the interface during epitaxial growth, leaving two long screw segments in their wake, some of which replicate through the interface and create IDs and HLAs. The driving force for the BPDs to glide toward the interface is thermal stress and driving force for the relaxation process to occur is the lattice parameter difference at growth temperature which results from the doping concentration difference between the substrate and epilayer. INTRODUCTION SiC has become the material of choice for high-temperature, high-frequency power devices. Realization of these devices require good control over the homoepitaxial growth. It is well known that basal plane dislocations (BPDs) present in CVD grown homo-epitaxial layers of 4H-SiC can have a detrimental effect on device performance [2-4] by inducing the expansion of Shockley faults in the epilayer which cause forward voltage drop. Previously it was thought that these BPDs are produced in the epilayers via replication processes occurring at the surface intersections of BPDs in the Physical Vapor Transport (PVT) grown 4H-SiC substrates. Consequently, one of the approaches adopted to mitigate this problem was to engineer the processes by which BPDs are replicated into the epilayer at their substrate surface intersections. For example, the conversion of BPDs into less harmful TEDs at the substrate/epi interface can be enhanced by direct etching of the substrate surface intersections of the BPDs [5,6] or by growth interrupts which induce etching [7]. Conversion rates of up
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