Design of High-Speed Binary Counter Architecture for Low-Power Applications
This chapter presents a design of high-speed binary counter architecture using clock gating for low-power applications. Clock gating techniques enables in improving the latency and power dissipation of proposed binary counter. The latency of proposed arch
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Abstract This chapter presents a design of high-speed binary counter architecture using clock gating for low-power applications. Clock gating techniques enables in improving the latency and power dissipation of proposed binary counter. The latency of proposed architecture is lower as compared to conventional architecture, which shows that the proposed design can be operated at high input frequencies. The proposed binary counter design of 4-, 8-, and 16-bit has been built by Verilog HDL code and simulated using Questa Simulator of Mentor Graphics. For synthesis of proposed design, LeonardoSpectrum tool by mentor Graphics is used and synthesis of it is based on CMOS process TSMC 0.35 µm, Spartan 6, and Spartan 3E FPGA. The Semicustom physical layout for Proposed 8-bit counter architecture using 350-nm Standard CMOS process is also obtained in this work. Keywords Binary counter · Clock gating · Latency · Power dissipation · Operating frequency · FPGA · Layout · Verilog HDL
1 Introduction In many VLSI system, binary counters are basic building blocks. A n-bit binary counter design consist a series of k-flip-flops, and its count value can be 0to(2k − 1) [1]. Fast binary counter design is the basic point of concern, when designing of high-speed digital system for various applications. Such as counting time for process allocation in scheduling, analog to digital conversion [2–4], time to digital M. D. Gupta (B) · S. K. Singh · R. K. Chauhan Department of Electronics and Communication Engineering, MMMUT, Gorakhpur, U.P, India e-mail: [email protected] S. K. Singh e-mail: [email protected] R. K. Chauhan e-mail: [email protected] © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 V. Nath and J. K. Mandal (eds.), Nanoelectronics, Circuits and Communication Systems, Lecture Notes in Electrical Engineering 692, https://doi.org/10.1007/978-981-15-7486-3_13
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conversion [5–9], etc. It can be used as clock dividers (used in on-chip processor because sometimes processor work at lower processor than actual frequency of the processor), etc. Design techniques of counter based on clock gating are categorized into asynchronous and synchronous counter. In synchronous counter, all flip-flops are operated by same clock pulse; however, in asynchronous counters design, LSB flipflop operated by master clock signal and output of each flip-flop act as a clock signal for succeeding flip-flops. Asynchronous counters are fundamentally different from synchronous counter because it can offer advantages [10] in the following areas such as low power dissipation; high operating speed; improved composability and modularity; no clock skew and clock distribution problems. Performance of synchronous counter such as delay is dependent on the counter bit length, thus latency of synchronous counter increases linearly with bit length. Another major issue, when modulus counters system is made by synchronous counters, is that it requires the fast dete
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