Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications
- PDF / 2,032,568 Bytes
- 12 Pages / 432 x 648 pts Page_size
- 8 Downloads / 136 Views
Development of high k/III-V (InGaAs, InAs, InSb) structures for future low power, high speed device applications Edward Yi Chang,1,2,*) Hai-Dang Trinh1, Yueh-Chin Lin1, Hiroshi Iwai3, and Yen-Ku Lin1 1
Department of Materials Science and Engineering, National Chiao Tung University, Taiwan. Department of Electronic Engineering, National Chiao Tung University, Taiwan. 3 Frontier Research Center, Tokyo Institute of Technology, Tokyo , Japan *) Email: [email protected]. 2
ABSTRACT III-V compounds such as InGaAs, InAs, InSb have great potential for future low power high speed devices (such as MOSFETs, QWFETs, TFETs and NWFETs) application due to their high carrier mobility and drift velocity. The development of good quality high k gate oxide as well as high k/III-V interfaces is prerequisite to realize high performance working devices. Besides, the downscaling of the gate oxide into sub-nanometer while maintaining appropriate low gate leakage current is also needed. The lack of high quality III-V native oxides has obstructed the development of implementing III-V based devices on Si template. In this presentation, we will discuss our efforts to improve high k/III-V interfaces as well as high k oxide quality by using chemical cleaning methods including chemical solutions, precursors and high temperature gas treatments. The electrical properties of high k/InSb, InGaAs, InSb structures and their dependence on the thermal processes are also discussed. Finally, we will present the downscaling of the gate oxide into sub-nanometer scale while maintaining low leakage current and a good high k/III-V interface quality. INTRODUCTION High-k/III-V structure has been extensively studied recently in order to realize the 16 nm node and beyond complementary metal-oxide-semiconductor (MOS) technology due to their high carrier mobility and drift velocity. Since the devices have been getting smaller, the requirement for the devices is not only high performance but also low power consumption. In this context, the III-V based devices emerge as a potential candidate which could allow to have very high performance at low supply voltage. Regardless of long term study, many issues on high k/III-V structure still need to be addressed. The density of state at high k/III-V interface is away high due to the poor III-V native oxide quality as well as high defect (vacancies, dangling bonds, like-atoms bonds) at III-V surfaces. The defect in high k oxide is also a problem which affects the performance of devices. Besides, the downscaling the equivalent oxide thickness into sub-nanometer with appropriate leakage current is also an important issue. In this paper, we present our effort including surface treatment, annealing treatment processes to deal with those issues. InGaAs, InAs and InSb based MOSCAP structures with Al2O3 and HfO2 high k oxides are focused in the study. EXPERIMENTAL PROCEDURE The MOSCAP structures used in this study is shown in Fig. 1. For InGaAs and InAs based devices, the wafers consist of 5×1017 cm-3 Si-doped n-type 100nm In0.53Ga0
Data Loading...
