Field-Programmable Gate Arrays in Embedded Systems
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Editorial Field-Programmable Gate Arrays in Embedded Systems Miriam Leeser,1 Scott Hauck,2 and Russell Tessier3 1 Department
of Electrical and Computer Engineering, Northeastern University, Boston, MA 02115, USA of Electrical Engineering, University of Washington, Seattle, WA 98195-2500, USA 3 Department of Electrical and Computer Engineering, University of Massachusetts, Amherst, MA 01003, USA 2 Department
Received 13 July 2006; Accepted 13 July 2006 Copyright © 2006 Miriam Leeser et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.
Welcome to the special issue on field programmable gate arrays (FPGAs). FPGAs are becoming an increasingly important part of embedded systems, as the collection of papers in this issue illustrates. “An overview of reconfigurable hardware in embedded systems” provides a comprehensive overview of the state-ofthe-art use of reconfigurable hardware in embedded systems. A detailed discussion of the use of FPGAs for application areas such as encryption, software-defined radio, and robotics is provided. Additionally, a concise assessment of design issues and current design tools is included. A sizable collection of citations provides a handy reference for newcomers to the field. The remaining papers address applications and tools for embedded systems design. The applications presented here are typical of the spectrum of FPGA applications. They fall into the categories of multimedia processing, including video, image and speech processing, as well as communications applications. The implementation of an MPEG-4 image encoder using a scalable number of Altera NIOS soft processors is presented in “Scalable MPEG-4 encoder of FPGA multiprocessor SOC.” An image is partitioned so that each processor receives a horizontal slice of the image. The author’s own on-chip interconnection network is used to connect the soft processors. The authors demonstrate a significant application speedup as additional soft processors are added to the FPGA platform. In “A real-time wavelet domain video denoising implementation in FPGA,” the authors present a two-FPGA solution for performing video denoising via a 3D (two spatial and one temporal dimension) wavelet filter. By careful consideration of the algorithm, data movement, and pipelining, a complete and complex image processing pipeline is produced.
In “A dynamic reconfigurable hardware/software architecture for object tracking in video streams,” the authors present a feature tracker that has been implemented on an FPGA. The authors focus on choosing an algorithm that is well matched to reconfigurable hardware, hardware/software partitioning, and efficient use of memory structures. Their implementation, which runs faster than a software-only solution, has applications for mobile autonomous platforms. The paper “Speech silicon: an FPGA architecture for realtime hidden Markov model-based speech recogni
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