Gate Oxide Integrity for Polysilicon Thin-film Transistors: A Comparative Study for ELC, MILC, and SPC Crystallized Acti
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Gate Oxide Integrity for Polysilicon Thin-film Transistors: A Comparative Study for ELC, MILC, and SPC Crystallized Active Polysilicon Layer D. C. Choi, B. D. Choi, J. Y. Jung, H. H. Park, J. W. Seo, K. Y. Lee, and H. K. Chung Advanced Technology Institute Samsung SDI Giheung, Yongin, Kyoungki 442-391, S. Korea ABSTRACT In this paper, we present the results of Plasma Enhanced Chemical Vapor Deposition gate oxide (SiO2) integrity on ELC (excimer laser crystallized), MILC (metal induced lateral crystallized) and SPC (solid phase crystallized) polysilicon films. We observed that gate oxide strength of poly Si TFT strongly depends on the crystallization method for the active silicon layer. In the case of ELC films, asperities on the silicon surface reduce the SiO2 breakdown field significantly. The metallic contaminants in MILC films are responsible for a deleterious impact on gate oxide integrity. Among the three cases, the SiO2 breakdown field was the highest for the SPC silicon films. The breakdown fields at the 50% failure points in Weibull plots for the ELC, MILC and SPC cases were 5.1MV/cm, 6.2MV/cm, 8.1MV/cm, respectively. We conclude that the roughness and metallic contamination of the poly Si films are the main factors that cause enhanced breakdown of SiO2 films. INTRODUCTION Of the several low temperature polysilicon (LTPS) technologies developed, the ELC technology is the most suitable method for poly Si TFT manufacturing due to its ability to crystallize silicon films without raising the substrate temperature significantly. However, the ELC poly Si have several limitations such as high cost, manufacturing difficulties, and observation of laser scan lines on the finished display products. Because of these limitations, many companies are turning to alternative non-laser crystallization techniques such as MIC, MILC, and SPC. In addition, recently, there is a need for reduction in device feature length and related dimensions for applications such as system-on-panels. For this reason, LTPS TFTs have been extensively studied for fabrication of the drivers, digital-to-analog converters (DACs), and timing controllers.1) Their reliability thus has a direct impact on the product lifetime. One of the most important reliability parameters is gate oxide integrity (GOI), which is the ability of a metal oxide semiconductor (MOS) device to remain operational for many years with the gate voltage applied.2, 3) The breakdown electric field of thermally grown silicon dioxide insulator used in integrated circuits is typically around 10-15MV/cm while that of PECVD SiO2 insulator used in LTPS TFTs is around 4-10MV/cm.3) The breakdown field of the deposited insulator depends on polysilicon surface roughness, crystal originated pits (COPs), and metallic precipitates as these are responsible for local high electric fields.2) The low breakdown electric field of insulator deposited using Plasma Enhanced Chemical Vapor Deposition (PECVD) is also attributed to porous oxides contaminated with metallic or ionic impurities and whic
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