Mechanical-Stress-Controlled Silicide Interconnections for Highly Reliable Semiconductor Devices
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Mechanical-Stress-Controlled Silicide Interconnections for Highly Reliable Semiconductor Devices Hiromi Shimazu and Hideo Miura Mechanical Engineering Research Laboratory, Hitachi, Ltd. 502 Kandatsu, Tsuchiura, Ibaraki 300-0013, Japan ABSTRACT Mechanical stress develops in silicide interconnection structures due to the volumetric shrinkage of newly grown silicide film during silicidation. Silicidation-induced stress of about 1 GPa was measured by inducing a reaction between a silicon wafer and a titanium film deposited on the wafer. The stress developed near the interface between the grown silicide film. The remaining silicon was analyzed using a finite-element method. The critical stress for delamination at the interface was determined by comparing the results of the estimated stress at the interface with the cross-sectional observation results of different interconnection-structures test samples. We also determined the critical thickness of TiSi 2 and the diameter of silicide contacts for eliminating delamination at the interface. INTRODUCTION In deep-submicron devices, the thickness and width of interconnections have been decreasing to enable using smaller devices. However, this reduction of cross sections increases interconnection resistivity. Thus, finding new materials with lower resistivity than conventionally used materials, such as polycrystalline silicon and aluminum alloys is important. Minimizing contact resistivity between the metals and silicon substrate is also important because of a Schottky barrier between the materials and the substrate. To minimize the effects of the barrier, metal silicides can be effectively used as interlayers. These interlayers are easy to form by inducing a reaction between the metals and silicon at temperatures below 700 oC, when the dopant in the silicon substrate does not diffuse much. Titanium silicide has widely been used among metal silicides, because its thermal reliability is higher than other metal silicides, such as nickel silicide and cobalt silicide [1]. However, silicidation also causes high stress due to the volume shrinkage of newly grown silicides during a metal reaction on silicon [2][3]. As a result, silicidation sometimes causes delamination between the reacted silicide and remaining silicon. To eliminate the delamination at the interface, we measured the stress during silicidation annealing by detecting changes in the curvature of the silicon wafers on which titanium film was deposited. We analyzed the stress distribution near the interface by using a finite-element method. By comparing the estimated results with the observation results of the reacted interface in the test samples, we determined the critical stress for delamination and the critical thickness and diameter of the contacts for eliminating delamination at the silicide/silicon interface to improve device reliability. B13.5.1 Downloaded from https:/www.cambridge.org/core. University of Arizona, on 19 Apr 2017 at 08:52:22, subject to the Cambridge Core terms of use, available at https:/www.cambri
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