Multi-Net Optimization of VLSI Interconnect
This book covers layout design and layout migration methodologies for optimizing multi-net wire structures in advanced VLSI interconnects. Scaling-dependent models for interconnect power, interconnect delay and crosstalk noise are covered in depth, and se
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ti-Net Optimization of VLSI Interconnect
Multi-Net Optimization of VLSI Interconnect
Konstantin Moiseev • Avinoam Kolodny Shmuel Wimer
Multi-Net Optimization of VLSI Interconnect
Konstantin Moiseev Intel Haifa, Israel
Avinoam Kolodny Technion Haifa, Israel
Shmuel Wimer Bar-Ilan University Ramat-Gan, Israel
ISBN 978-1-4614-0820-8 ISBN 978-1-4614-0821-5 (eBook) DOI 10.1007/978-1-4614-0821-5 Springer New York Heidelberg Dordrecht London Library of Congress Control Number: 2014953304 © Springer Science+Business Media New York 2015 This work is subject to copyright. All rights are reserved by the Publisher, whether the whole or part of the material is concerned, specifically the rights of translation, reprinting, reuse of illustrations, recitation, broadcasting, reproduction on microfilms or in any other physical way, and transmission or information storage and retrieval, electronic adaptation, computer software, or by similar or dissimilar methodology now known or hereafter developed. Exempted from this legal reservation are brief excerpts in connection with reviews or scholarly analysis or material supplied specifically for the purpose of being entered and executed on a computer system, for exclusive use by the purchaser of the work. Duplication of this publication or parts thereof is permitted only under the provisions of the Copyright Law of the Publisher’s location, in its current version, and permission for use must always be obtained from Springer. Permissions for use may be obtained through RightsLink at the Copyright Clearance Center. Violations are liable to prosecution under the respective Copyright Law. The use of general descriptive names, registered names, trademarks, service marks, etc. in this publication does not imply, even in the absence of a specific statement, that such names are exempt from the relevant protective laws and regulations and therefore free for general use. While the advice and information in this book are believed to be true and accurate at the date of publication, neither the authors nor the editors nor the publisher can accept any legal responsibility for any errors or omissions that may be made. The publisher makes no warranty, express or implied, with respect to the material contained herein. Printed on acid-free paper Springer is part of Springer Science+Business Media (www.springer.com)
To our many Intel colleagues and friends, who taught us and learned from us.
Preface
Interconnect has become a crucial element in advanced electronic systems. State-ofthe-art CMOS processes utilize 10 or more layers of metal above the active transistors, so these interconnect layers dominate processing costs. In recent years, interconnect power and interconnect delay have become major limiters for VLSI technology. Interconnect engineering—designing on-chip wires to satisfy performance requirements while meeting power, reliability, and cost specifications—is currently one of the most challenging tasks faced by product development teams. Significant difficulties arise because tradition
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