Photo-Induced Large Area Growth of Dielectrics With Excimer Lamps
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1.
Introduction
As dynamic random access memories (DRAMs) are scaled down, the thickness of Si0
2
gate oxide must be
correspondingly reduced and thickness control becomes a critical issue. The projected silicon dioxide (SiO 2 ) thickness by 2012 predicted by the semiconductor industry roadmap will reach atomic dimensions (five silicon atomic layers), or less than one nanometre [11 as indicated in Table 1 [2-3]. As can be seen, for 0.1 pm ultra-large-scale-integrated (ULSI) device technologies, the SiO, gate oxide thickness must be scaled below 2.0 nm and become so thin that direct tunneling effects and excessively high electric fields become serious obstacles to reliability as well as fundamental quantum mechanical difficulties. What is required is a thicker layer of a higher dielectric constant material that will have the same or similar effective capacitance when it is put into a device and enable a further decrease in device area (see table 1). Table I. The projected gate oxide thickness for CMOS integrated circuitsfor 1997-2012 [2-31
Technology timeline
1997
1999
2001
2003
2006
2009
2012
Design rule (pm) Wafer diameter (mm) Gate dielectric (nm. E=3.9) equivalent SiO 2
0.25 200 4-5
0.18 300 3-4
0.15 300 2-3
0.13 300 2-3
0.10 300 1.5-2
0,07 450 .
2.2
Ta
40
20
.C
21
02°°0°0°°°°°°°°°°°°
) 2.1
20 25 30 10 15 Sputtering time (miin) Fig. 2 XPS profile of a 14 mn tantalum oxide film formed on silicon at 450'C with afixed irradiationtime of 20 min 0
5
9
2
20
0
10 6 8 2 4 Distance across 4 inch wafer (cm) Fig. 3 Thickness and refractive index of the films formed across a 4 inch silicon wafer by irradiatingat 350°C for 15 min. 0
Figure 3 shows the thickness and refractive index of layers formed on a 4 inch silicon wafer by irradiating spin-coated films at a temperature of 350'C for an exposure time of 15 min. As can been seen, very uniform films (about 22.6 nm) were achieved with the total variation in thickness across the 4-inch wafer being within ± 0.2 nm. The mean refractive index measured (2.15) was similar to that usually obtained for plasma-deposited Ta 2 0 5 films [29]. XRD revealed the structure of films formed to be amorphous. Table 5 Comparisonof the electricalproperties of the as grown Ta205films at different temperatures 2 2 Leakage current density at 0.5 MV/cm (A/cm ) Fixed charge density (cm- ) Temperature (°C)
150
4.0 x 1011
5 1.9 x 10-
250
2.6 x 10o1
9.2 x 10-6
400
1.0 x 1011
9.0 x 10-8
120
Metal oxide semiconductor (MOS) capacitors have been fabricated using 20 nm thick as grown Ta2 0 5 layers formed by this process. Table 5 shows a comparison of the electrical properties in our films formed at different temperatures. It can be seen that the fixed oxide charge density decreases with increasing temperature. The fixed oxide charge density 2 2 changed from 4.0 x 10'' cm- at 150°C to 1.0 x 1011 cm- at 400'C, which is similar to those obtained in the films prepared by plasma-CVD processing [103]. The I-V characteristics of the MOS capacitors also showed that the
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