Read Back of Stored Data in Non Volatile Memory Devices by Scanning Capacitance Microscopy
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Read Back of Stored Data in Non Volatile Memory Devices by Scanning Capacitance Microscopy Rudra S. Dhar1, St.J. Dixon-Warren2, Mohamed A. Kawaliye2, Jeff Campbell2, Mike Green2, and Dayan Ban1 1 Department of Electrical & Computer Engineering, Waterloo Institute for Nanotechnology, University of Waterloo, 200 University Ave W., Waterloo, ON, N2L3G1, Canada 2 Chipworks, 1891 Robertson Road, Suite 500, Ottawa, ON K2H 5B7, Canada ABSTRACT This report outlines a methodology for reading back different electrical charges, from Non Volatile Memory (NVM) based Flash devices. The charge is stored in the floating gates (FGs) of the transistors. Reading back these charges in the form of logic levels of “1 bit (1b)” and “0 bit (0b)” without deleting the information from the device was the goal. Scanning Capacitance Microscopy (SCM) with ~50-100 nm spatial resolution was used, to directly probe the charge on Floating Gate Transistor (FGT) channels. Transistor charge values (ON/OFF or “1b/0b”) are measured. Both the sample preparation and SCM probing methods are discussed. The application has been demonstrated with SanDisk based 64 MB NAND Flash memory device. INTRODUCTION Non Volatile Memory (NVM) devices have been used for many important civilian, space and military applications such as storage of mission parameters data and the communication algorithms. The data is stored as different electrical charges in the floating gates (FGs) in NVM device that represent in logic levels “1b” and “0b”. The conventional approach for memory readback and device failure analysis is through a combination of multiple-steps of circuit reverse engineering followed by electronic extraction of the stored code from the memory. This is considered to be an indirect approach of reading the stored data. The motivation to measure the on-site programmed charges in the NVM devices is highly advantageous, which could directly reveal the programmed charges, categorizing opposite logic levels, “1b” and “0b” that are programmed in fully functional nominal bit lines [1]. On the basis of the work done by Skorobogatov et al. [3], Nardi et al. [1] considered accuracy between 103 and 105 electrons for standard 5V EEPROM cell, causing a 3.5V shift in threshold voltage. The charge density can be measured by directly probing the device on site using physical measurement techniques [2]. This is possible with electrical techniques like SCM or SKPM based on the AFM system that has high spatial resolution (~15 nm for SCM and ~40 nm for SKPM) and can identify the carrier concentration determining the logic value of each memory bit. The AFM based measurements can be correlated to the logic programming of the memory by constructing words or bit lines [2]. The NVM programming principles is presented in this report along with the utilities for programming the device that varies depending on the kind of device; in this case it is a discrete Flash memory. IC de-processing is followed thereafter which is one of the most significant prerequisites [2]. Preparing the device with suc
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