Semiconductor Dopant Profile and Dielectric Characterization with Scanning Capacitance Microscopy
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Semiconductor Dopant Profile and Dielectric Characterization with Scanning Capacitance Microscopy J. J. Kopanski Semiconductor Electronics Division, National Institute of Standards and Technology, Gaithersburg, MD 20899-8120, U.S.A.
ABSTRACT Scanning capacitance microscopy (SCM) has been commonly used to image dopant gradients in silicon and other semiconductors. As a mobile, high-resolution (to 10 nm) metaloxide-semiconductor (MOS) probe, SCM also is a non-destructive, contactless tool with which to examine local variations in dielectric thin film quality and local variations in semiconductor substrate properties. Virtually any measurement that can be made with fabricated metal electrodes can also be made with SCM. Two particular applications being pursued are characterization of high-κ dielectric films on silicon for next generation integrated circuits and characterization of native and deposited insulators on wide bandgap semiconductors. Local differential capacitance (∆C) versus tip bias (Vdc) measurements can be made with SCM using an ac voltage to generate the differential capacitance signal. These measurements differ from conventional C-V measurements due to the 3-D nature of the scanning capacitance microscope tip and the method used to generate the differential capacitance signal. Theoretical predictions and experimental measurements are made of SCM differential capacitance versus dc bias voltage (∆C-V) curves for MOS capacitors with various levels of fixed and interface traps. The goal of this work is to determine if quantitative interface trap distributions can be made using SCM and if variations in interface density can be observed near defects or device structures. The response of the SCM MOS capacitance measurement to a local electric field stress and optical pumping from the atomic force microscope (AFM) laser will also be discussed.
INTRODUCTION Since becoming available as a commercial tool, the scanning capacitance microscope has been increasingly employed by the semiconductor industry for qualitative inspection and failure analysis. Scanning capacitance microscopy (SCM) measures and produces images of the differential capacitance generated by an ac bias voltage, ∆C(Vac), between the metallic SCM tip and a semiconductor sample. The ∆C signal depends on the generation and modulation of a depletion region in the semiconductor sample. For silicon, this usually requires the presence of a thin (2 nm to 5 nm) silicon dioxide (SiO2) layer on the sample surface so that the SCM tip can form a metal-oxide-semiconductor (MOS) capacitor with the silicon. ∆C is to lowest order proportional to the inverse of the square root of the dopant concentration in the semiconductor in the vicinity of the SCM tip. SCM images of cross-sectioned metal oxide semiconductor field effect transistors (MOSFETs) clearly show contrast proportional to the dopant concentration in the source/drain, and channel regions, which can be quantitatively interpreted to find the twodimensional (2-D) dopant profiles of the source/drain
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