The Electrical Characterization of Molecular-Beam-Deposited LaAlO 3 on GaAs and its Annealing Effects
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The Electrical Characterization of Molecular-Beam-Deposited LaAlO3 on GaAs and its Annealing Effects Donghun Choi1, Maitri Warusawithana2, Chi On Chui3,4, Joseph Chen5, Wilman Tsai4, Darrell G. Schlom2, and James S. Harris1 1 Electrical Engineering, Stanford University, Stanford, CA, 94305 2 Materials Science and Engineering, Pennsylvania State University, University Park, PA, 168025005 3 Electrical Engineering, University of California, Los Angeles, Los Angeles, CA, 90095 4 Intel Corporation, Santa Clara, CA, 95052 5 Materials Science and Engineering, Stanford University, Stanford, CA, 94305 ABSTRACT The electrical properties of Al/LaAlO3/GaAs metal-oxide-semiconductor capacitors were investigated. A thick arsenic (As2) capping layer was used to protect the GaAs surface from oxidation and contamination during the air exposure that occurred between the deposition of the GaAs and LaAlO3 layers in different molecular-beam epitaxy systems. Amorphous LaAlO3 was deposited on c(4◊4) - and (2◊4) - reconstructed (100) GaAs surfaces. Post dielectric deposition annealing was found to improve the capacitance-voltage (C-V) characteristics by eliminating frequency dispersion in the depletion and weak inversion regimes and diminished the bidirectional C-V hysteresis to 210 mV. Reasonably low gate leakage current was maintained after annealing. INTRODUCTION One of the approaches to realize low power and high-speed/frequency devices is using materials in which the carrier mobility is much higher than that of silicon, such as gallium arsenide (GaAs). For the past three decades, however, the lack of useful surface passivation for compound semiconductors has precluded development of metal-oxide-semiconductor (MOS) devices and caused high surface recombination parasitic in scaled devices. The oxidation and the metal deposition on III-V materials create a high interfacial trap density (Dit); the former by causing the considerable local lattice rearrangement and the latter by disturbing the periodic structure at the surface.[1, 2] Extra metallic arsenic (As) atoms on the surface also lead to high Dit.[3] The accelerated recombination velocity due to surface/interface defects pins the Fermi level near the energy bandgap center. In the case of a metal-oxide-semiconductor field effect transistor (MOSFET), the Fermi level pinning prevents the modulation of the surface potential with gate bias voltage. Thus, development of high performance GaAs-based MOS device applications demands new surface treatment techniques and materials to reduce the Dit. In addition, a new high dielectric constant material is essential to decrease the gate leakage current and enable the continuation of MOS scaling. Many insulators, such as Ga2O3(Gd2O3)[4], Al2O3[5], HfO2[6] are currently being explored. Here, we investigate the use of molecular beam deposited (MBD) lanthanum aluminate (LaAlO3) on GaAs using an As capping layer to protect surface while moving the samples from the GaAs molecular-beam epitaxy (MBE) system to the LaAlO3 molecular-beam deposi
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