Using Wafer-Scale Patterns for CMP Analysis
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Using Wafer-Scale Patterns for CMP Analysis Brian Lee1, Terence Gan , Duane S. Boning1, Jeffrey David2, Benjamin A. Bonner2, Peter McKeever2, and Thomas H. Osterheld2 1 Massachusetts Institute of Technology, Cambridge MA 2 Applied Materials, Santa Clara, CA 1
ABSTRACT A new set of wafer-scale patterns has been designed for analysis and modeling of key CMP effects. In particular, the goal of this work is to develop methods to characterize the planarization capability of a CMP process using simple measurements on wafer scale patterns. We examine means to pattern large trenches (e.g. 1 to 15 mm wide and 15 mm tall) or circles across 4” and 8” wafers, and present oxide polish results using both stacked and solo pads in conventional polish processes. We find that large separation (15 mm) between trenches enables cleaner measurement and analysis. Examination of oxide removal in the center of the trench as a function of trench width shows a saturation at a length comparable to the planarization length extracted from earlier studies of small-scale oxide patterns. Increase in polish pressure is observed to decrease this saturation point. Such wafer scale patterns may provide information on pad flexing limits in addition to planarization length, and promise to be useful in both patterned wafer CMP modeling and studies of wafer scale CMP dependencies such as nanotopography. INTRODUCTION Current techniques for characterizing CMP typically involve patterning test dies onto a wafer, running polish experiments, and analyzing measurements to obtain characterization parameters for the process [1]. A key parameter known as planarization length is typically used to describe the length scale over which feature-induced pattern density on the wafer affects the polishing at a particular point on the die. By adding feature-scale step-height considerations to planarization length-based density evaluation, accurate models of post-CMP oxide thickness (with ~100 Angstrom error) have been demonstrated for conventional stacked pads and processes [2]. An alternative approach using wafer-scale patterns has previously shown promise as a tool to study CMP pattern dependencies [3]. With an increased interest in harder polishing pads (to increase planarization length and reduce within-die variation), the planarization length is approaching the size of the typical die. In addition, harder pads may induce a “pad flexing limit” in which the contact of the pad in large “low” regions of the die is decreased. For these reasons, as well as interest in simplified measurement and analysis of planarization length, wafer-scale patterns for detailed CMP planarization characterization are explored further in this work. In the next section, we describe new mask designs for wafer-scale patterns. Key issues include the range of trench (or circle) sizes that should be included, as well as the separation between them on the wafer. In addition, we describe two patterning methods used here, including traditional mask plates and acetate-based masks. The following section
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