Silicon Carbide Hot-Wall Epitaxy for Large-Area, High-Voltage Devices
- PDF / 177,644 Bytes
- 7 Pages / 612 x 792 pts (letter) Page_size
- 43 Downloads / 196 Views
1069-D04-01
Silicon Carbide Hot-Wall Epitaxy for Large-Area, High-Voltage Devices M. J. O'Loughlin, K. G. Irvine, J. J. Sumakeris, M. H. Armentrout, B. A. Hull, C. Hallin, and A. A. Burk, Jr. Cree, Inc., 4600 Silicon Dr., Durham, NC, 27703 ABSTRACT The growth of thick silicon carbide (SiC) epitaxial layers for large-area, high-power devices is described. Horizontal hot-wall epitaxial reactors with a capacity of three, 3-inch wafers have been employed to grow over 350 epitaxial layers greater than 100 µm thick. Using this style reactor, very good doping and thickness uniformity and run-to-run reproducibility have been demonstrated. Through a combination of reactor design and process optimization we have been able to achieve the routine production of thick epitaxial layers with morphological defect densities of around 1 cm-2. The low defect density epitaxial layers in synergy with improved substrates and SiC device processing have resulted in the production of 10 A, 10 kV junction barrier Schottky (JBS) diodes with good yield (61.3%). INTRODUCTION In recent years, there has been significant progress in the development of silicon carbide (SiC) power devices. SiC Schottky Diodes with blocking voltages between 300 and 1200 V are commercially available, and higher voltage devices are being introduced or developed. There have been some demonstrations of high-voltage diodes using SiC, but in most instances these have been small area devices [1]. The ultimate benefits of using SiC for high-voltage diodes can only be achieved with large-area, high-current devices. For example, Cree’s 1200 V-50 A Schottky diodes have an active device area of 0.33 cm2 [2], and we have demonstrated 10 kV, 20 A junction barrier Schottky (JBS) diodes with an active area of 1.5 cm2 [3]. To achieve significant yields of these large area devices, defect densities of less than 1 cm-2 are necessary. These low defect densities have been achieved only through significant advances in substrate and epitaxial layer quality. The subject of this paper will be the development of hot-wall epitaxy reactors and process capability to grow large quantities of low-defect, uniform SiC epitaxial layers greater than 100 µm thick. The hot-wall epitaxy reactors that we employ have a capacity of three, 3-inch diameter wafers. For epilayers thicker than about 25 µm, we typically grow on 8° off-axis substrates although we are not constrained by that angle. For both p and n-type intentional doping, layers can be reproducibly grown from 2x1014 to over 1x1019 cm-3, permitting complex structures, like GTOs, to be grown in a continuous run. Thickness and doping uniformity are generally on the order of 1% or better and 5-8% (std. dev./mean), respectively. Most pertinent to the theme of this presentation, we utilize an optimized buffer process to dramatically reduce the density of morphological defects, particularly “carrot” defects, in subsequent layers [4]. Using this process, we have grown hundreds of thick epilayers with a median defect density of 1.38 cm-2 (including substra
Data Loading...
