• PDF / 410,493 Bytes
• 6 Pages / 612 x 792 pts (letter) Page_size
• 72 Downloads / 240 Views

DOWNLOAD

REPORT

---

B9.9.1

The Effect of Immersion Sn coating on the Electromigration Failure Mechanism and Lifetimes of Cu Dual Damascene Interconnects Minyu Yan 1, King-Ning Tu1, Anand V. Vairagar 2, 3, Subodh G. Mhaisalkar 2 and Ahila Krishnamoorthy 3 1 Department of Materials Science and Engineering, UCLA, 6532 Boelter Hall, 405 Hilgard Ave, Box 951595, Los Angeles, CA 90095-1595, U.S.A. 2 School of Materials Engineering, Nanyang Technological University, N4.1-B3-02, 50 Nanyang Avenue, 639798 Singapore. 3 Institute of Microelectronics, 11 Science Park Road, Singapore Science Park II, 117685 Singapore. ABSTRACT In sub-micron dual damascene Cu interconnects, electromigration occurs mainly along the interfaces between Cu and dielectric cap layer. Many reports have shown that the interface of Cu/dielectric cap is the dominant diffusion path. In-situ electromigration experiments were carried out recently by A. V. Vairagar etal [APPL. PHYS. LETT., 85, 2502 (2004)] to investigate the electromigration failure mechanisms in the upper and lower layers in dualdamascene Cu test structures. It was found that electromigration-induced void first nucleates at locations which are far from the cathode, then moves along the Cu/dielectric cap interface in opposite direction of electron flow, and eventually causes void agglomeration at the via in the cathode end to open the interconnect. In the present study, immersion Sn (20 nm) was employed after CMP and before SiN deposition. All the samples, with a line-width of 0.28 um, were assessed by package level electromigration tests at 300°C under a current density of 3.6MA/cm2. We found that immersion Sn surface treatment effectively introduced the Cu-Sn bonding to the Cu/dielectric interface and has influenced electromigration along the Cu/dielectric interfaces. Failure analysis shows that the samples with these Sn processes have a median-time-to-failure almost 1 order of magnitude larger than the control samples. A careful characterization utilizing FIB and SEM cross-sectional images shows that the failure mechanism has changed due to the Sn surface treatments. After electromigration-induced void nucleation, its movement is blocked by the strong Cu-Sn bonding so that its growth is localized and occurs along grain boundaries. With the increased impedance to surface diffusion, failure analysis seems to indicate that grain boundary diffusion now participates in the void movement and growth, which is proposed to be the reason for the increased lifetime.

INTRODUCTION With every new generation of microprocessors the number of transistors on a chip increases significantly. Today, more than 100 million field effect transistors are integrated on a single die. At the 90 nm CMOS technology node, advanced design incorporate up to 9 levels of copper interconnects with critical dimensions below 150 nm for the lower layers. Such a complex interconnect structures requires an extremely good reliability. Currently electromigration in dual-damascene Cu interconnects is one of the most important reliability issues in micr