The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs
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The Impact of Fermi Pinning on Thermal Properties of the Instabilities in ZnO TFTs R. B. M. Cross and M. M. De Souza Emerging Technologies Research Centre, De Montfort University, The Hawthorne Building, The Gateway, Leicester, LE1 9BH, United Kingdom
ABSTRACT In this paper we describe gate bias and temperature induced device instabilities of inverted-staggered ZnO-TFTs. It is shown that low positive and negative gate bias results in the transfer characteristics shifting in a positive and negative direction respectively. It is suggested that this is a consequence of temporary charge trapping at or close to the channel/insulator interface. The degradation of device parameters such as the threshold voltage, subthreshold slope and effective channel mobility is demonstrated at elevated measurement temperatures, suggesting the generation of defects and/or trap states in the interfacial region. In addition, it is postulated from the extracted activation energy of the drain current that the Fermi-level is pinned during the operation of the devices due to the high level of states close to the conduction band edge. These results highlight the relatively ease with which defects could be created at the interface, indicating a high concentration of weak or strained bonds. Both charge trapping and defect creation-induced instabilities appear to be reversible, as all devices regain their original characteristics after a period of relaxation at room temperature. INTRODUCTION There has been an emerging interest in flexible, lightweight electronics on plastic substrates which has motivated significant research on new materials and processes for the fabrication of thin film transistors (TFTs) [1][2]. The viable working temperatures of such substrates are usually limited to less than 150 °C, which raises serious compatibility issues for electronics based on silicon. This has lead to an increasing number of investigations into organic semiconductors and in particular oxide-based semiconductors as possible inexpensive alternatives [3-5]. One such material is zinc oxide (ZnO) and its related compounds. ZnO is a wide bandgap (~3.35 eV) semiconductor that can be deposited at low temperatures and over large areas using conventional fabrication methods. The fact that ZnO is also transparent in the visible range, and hence less light sensitive, raises the possible of truly transparent transistor structures. Recently, there have been a number of reports on ZnO-TFTs demonstrating high channel mobilities and on-currents [6-8] that are at least commensurate with and often in excess of those of industry-standard devices based on hydrogenated amorphous silicon (a-Si:H). However, very little is yet known of the stability of such devices [9]. The stability of TFTs is of fundamental importance for their exploitation and is a wellstudied topic in TFTs based on a-Si:H. The aim of this paper is to describe how gate bias stress and temperature can affect the device characteristics and parameters of ZnO-TFTs.
EXPERIMENT The TFT test structu
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