The Stepwise Cross-sectional Crystalline Analysis of the Stress Induced Voiding in Cu Interconnect
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0914-F07-04
The Stepwise Cross-sectional Crystalline Analysis of the Stress Induced Voiding in Cu Interconnect Hyo-Jong Lee, Heung Nam Han, Suk Hoon Kang, Jeong-Yun Sun, and Kyu Hwan Oh School of Materials Science and Engineering, Seoul National University, San 56-1, Shinrimdong, Kwanak-gu, Seoul, 151-744, Korea, Republic of
ABSTRACT In a crystallographic study of stress induced voiding of copper interconnect, the planar electron backscattered diffraction analysis showed that the void was initiated at the triple junction of the grain boundaries, not at the junction of the twin boundary and grain boundary. By using stepwise cross-sectional crystalline investigation for the void, it was possible to rebuild 3D crystalline structure near the void. From the stress calculation based on the measured crystalline structures, the hydrostatic stress was highly concentrated at the triple junction of the twin boundary and grain boundary, but experimentally, there was no voiding at that. The voiding in the copper interconnect may depend mainly on the boundary instability. INTRODUCTION Since IBM published the copper dual damascene process in 1997, almost all chipmakers have adopted the copper process in their logic devices based on the 130nm design rule. Moreover, in the next 90nm generation, low-k materials were also adopted. These replacements in the conducting and dielectric materials have needed various tests for the interconnect reliability, such as the electromigration (EM), bias temperature stressing (BTS) and temperature dependent dielectric breakdown (TDDB) tests. In addition to these three tests, the high temperature storage (HTS) test will also be very important, because stress induced voiding (SIV) by heat budget can cause interconnection failures during semiconductor processes. The purpose of the HTS test was to estimate the interconnection failure caused by heat treatments at about 150~300 ℃ for 100~1000 hrs. The failure analysis by using a focused ion beam (FIB) showed that a large void was generated at the position of a wide pattern which a via pattern contacts [1]. Therefore, many researchers have reported that the cause of the SIV is the stress concentration induced by the upper via pattern. Recently, Lee et al. suggested a new explanation of the SIV phenomenon [2]. They found that many voids were generated on a lower wide pattern after decapping the upper layers. The voids in the wide pattern were randomly generated and many of them were already generated before via etch process. Some voids seemed to be generated during the depositions of the etch stopping layer (ESL) and intermetallic dielectric (IMD). Therefore, interconnection failure occured in the wide line of the chain patterns, because stochastically one via in every few thousand was likely to come into contact with a void of the wide line.
Figure 1. Sample preparation, (a) cross-sectional structure of the sample after CMP, (b) deposition of capping layers of SiN and fluorinated silicate glass (FSG), (c) stripping of the capping layer after heat treat
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