Three-Dimensional Integration Technology for Advanced Focal Planes
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1112-E01-02
Three-Dimensional Integration Technology for Advanced Focal Planes Craig Keast, Brian Aull, Jim Burns, Chenson Chen, Jeff Knecht, Brian Tyrrell, Keith Warner, Bruce Wheeler, Vyshi Suntharalingam, Peter Wyatt, and Donna Yost Lincoln Laboratory, Massachusetts Institute of Technology 244 Wood Street, Lexington, MA 02420, USA ABSTRACT We have developed a three-dimensional (3D) circuit integration technology that exploits the advantages of silicon-on-insulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers. This paper describes the 3D technology and discusses some of the advanced focal plane arrays that have been built using it. INTRODUCTION Over the last several years MIT Lincoln Laboratory (MITLL) has developed a threedimensional (3D) circuit integration technology that exploits the advantages of silicon-oninsulator (SOI) technology to enable wafer-level stacking and micrometer-scale electrical interconnection of fully fabricated circuit wafers1. Advanced focal plane arrays have been the first applications to exploit the benefits of this 3D integration technology. The massively parallel information flow present in 2D imaging arrays maps very nicely into a 3D computational structure as information flows from circuit-tier to circuit-tier in the z-direction. To date, the MITLL 3D integration technology has been used to fabricate four different focal planes including: a 2-tier 64 x 64 imager with fully parallel per-pixel A/D conversion2; a 3-tier 640 x 480 imager consisting of an imaging tier, an A/D conversion tier, and a digital signal processing tier; a 2-tier 1024 x 1024 pixel, 4-side-abutable imaging module for tiling large mosaic focal planes3; and a 3tier Geiger-mode avalanche photodiode (APD) 3-D LIDAR array, using a 30 Volt APD tier, a 3.3 Volt CMOS tier, and a 1.5 Volt CMOS tier4. This last focal plane is an excellent example of one of the principal strengths of the 3D integration technology—the ability to integrate the best technology for the desired function within each tier of the circuit stack. This paper will provide a brief overview of MIT-LL’s 3Dintegration process, and discuss some of the focal plane applications where the technology is being applied including a mixed material short-wave infrared (SWIR) focal plane array. 3D TECHNOLOGY 3D focal planes and circuits are fabricated by transferring and interconnecting fully fabricated 150mm SOI substrates to a base wafer. The base wafer can be a high fill factor detector wafer or
another circuit wafer and does not have to be a SOI substrate. The assembly process and a 3D chip consisting of three tiers are shown in Figure 1.
Figure 1. Assembly process for a 3D chip: (a) Two completed circuit wafers are planarized, aligned, and bonded face to face; (b) the handle silicon is removed; (c) 3D vias are etched through the deposited BOX and the field oxides; (d) tungsten plugs are formed to connect circuits in both tiers; and (e) after tier 3 is transferred, bond pads
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