3-D Integration Technology for High Performance Detector Arrays
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0970-Y03-04
3-D Integration Technology for High Performance Detector Arrays Dorota Temple1, Christopher A. Bower1, Dean Malta1, James E. Robinson2, Phillip R. Coffman2, Mark R. Skokan2, and Terry B. Welch2 1 RTI International, Research Triangle Park, NC, 27709 2 DRS Infrared Technologies, Dallas, TX, 75374
ABSTRACT This paper describes a technology for three-dimensional (3-D) integration of multiple layers of silicon integrated circuits. The technology promises to dramatically enhance on-chip signal processing capabilities of a variety of detector devices hybridized with Si electronics. The focus of the paper is on high performance infrared focal plane arrays based on HgCdTe, which offer the ultimate in infrared sensitivity and find application in high performance military systems. Performance data from test FPA devices with integrated multilayer Si stacks are discussed in this paper. INTRODUCTION 3-D integration technology opens doors to unprecedented performance levels in imaging detectors. Performance characteristics impacted by this new approach are dynamic range, sensitivity, ability to combine active and passive imaging in one device, operation in multiple color bands, and on-chip “decision making”, among others [1-3]. The key enabling factor is the massively parallel signal processing capability inherent in 3-D device architectures. Figure 1 illustrates the conceptual transition from the state-of-the-art detector architecture, limited to two device layers, and interconnected either by metal bumps (A) or vertical interconnects through the
A
C B
Figure 1. Performance of state-of-the-art detector arrays hybridized to Si readout ICs (ROICs) (A, B) can be dramatically improved by the integration of multiple Si IC layers (C). The hybridization of the detector layer to the stacked ROIC can be performed using interconnects through the detector layer (as shown in C) or microbumps.
detector layer (B), to the structure consisting of multiple layers of Si ICs (C). When the integration is limited to two layers, the detector and one 2-D readout IC (ROIC), any signal processing circuitry needs to fit within the confines of the pixel. The 3-D integration revolutionizes the device architecture by allowing additional layers of silicon ICs to be incorporated (with optimal short interconnect paths and enormous inter-layer signal bandwidth), removing the IC real-estate limit and greatly enhancing functionality of the detector array. Further, different functions of the Si circuitry can be assigned to different layers, e.g. an analog amplifier IC can be separated from an analog-to-digital converter and from a digital processor. As these different ICs are based on different processes with different design rules, it is advantageous not to produce them in a monolithic form, but rather as separate components. Fabrication processes can then be optimized for the specific functionalities, resulting in increased yield and reduced cost. The benefits of the third dimension can be seen in a comparison of the physical attributes of a 2-
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