Floating Gate Devices: Operation and Compact Modeling
Floating Gate Devices: Operation and Compact Modeling focuses on standard operations and compact modeling of memory devices based on Floating Gate architecture. Floating Gate devices are the building blocks of Flash, EPROM, EEPROM memories. Flash memories
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Floating Gate Devices: Operation and Compact Modeling by
Paolo Pavan DII – Università di Modena e Reggio Emilia, Italy
Luca Larcher DISMI – Università di Modena e Reggio Emilia, Italy and
Andrea Marmiroli STMicroelectronics, Central R&D, Italy
KLUWER ACADEMIC PUBLISHERS NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
eBook ISBN: Print ISBN:
1-4020-2613-7 1-4020-7731-9
©2004 Springer Science + Business Media, Inc. Print ©2004 Kluwer Academic Publishers Dordrecht All rights reserved No part of this eBook may be reproduced or transmitted in any form or by any means, electronic, mechanical, recording, or otherwise, without written consent from the Publisher Created in the United States of America
Visit Springer's eBookstore at: and the Springer Global Website Online at:
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Contents
Contributing Authors
ix
Preface
xi
Foreword
xv
1. INTRODUCTION
1
1.
COMPACT MODELING General concepts and definitions The Compact Modeling of a Floating Gate Device 2. SEMICONDUCTOR MEMORIES 3. FLOATING GATE DEVICES 4. FIRST COMMERCIAL DEVICES AND PRODUCTS 5. EVOLUTION 6. APPLICATIONS AND MARKET CONSIDERATIONS 6.1 Applications 6.2 Market highlights REFERENCES 1.1 1.2
2. PRINCIPLES OF FLOATING GATE DEVICES 1. 1.1 1.2 1.3 1.4 1.5
TECHNOLOGY HIGHLIGHTS Introduction Lithography Field isolation Silicon oxidation Ion Implantation, Deposition, Etching, Chemical Mechanical Polishing, Metallization v
1 2 4 6 7 9 10 12 12 13 14
17 17 17 18 21 22 22
vi
CONTENTS 2.
CELL OPERATION Charge injection mechanisms Channel Hot Electron current CHannel Initiated Secondary ELectron current Fowler-Nordheim Tunneling Current 3. DISTURBS AND RELIABILITY 3.1 Programming Disturbs 3.2 Retention 3.3 Endurance 3.4 Erase Distribution 3.5 Scaling issues REFERENCES 2.1 2.2 2.3 2.4
3. DC CONDITIONS: READ 1.
TRADITIONAL FG DEVICE MODELS 1.1 The classical FG voltage calculation method 1.2 Drain current calculation 1.3 Limits of the capacitive coupling coefficient method 1.3.1 The capacitive coupling coefficient extraction procedure 1.3.2 The bias dependence of the capacitive coupling coefficients 2. THE CHARGE BALANCE MODEL 2.1 The Floating Gate voltage calculation procedure 2.2 Advantages and scalability 2.3 Parameter extraction 3. SIMULATION RESULTS REFERENCES
4. TRANSIENT CONDITIONS: PROGRAM AND ERASE 1. 2.
MODELS PROPOSED IN THE LITERATURE THE CHARGE BALANCE MODEL: THE EXTENSION TO TRANSIENT CONDITIONS 3. FOWLER-NORDHEIM CURRENT 3.1 Theory and compact modeling 3.1.1 Charge quantization effects on oxide barrier height 3.1.2 The oxide field calculation 3.2 Simulation Results 4. CHANNEL HOT ELECTRON CURRENT 4.1 Theory and Compact Modeling 4.1.1 The “lucky-electron” model 4.1.2 Alternative CHE current models 4.2 Simulation Results 4.3 CHISEL current modeling REFERENCES
24 24 25 27 27 29 30 30 32 32 33 34
37 37 38 39 40 41 42 43 45 46 46 47 54
57 57 60 61 61 63 65 70 74 74 75 77 80 82 83
CONTENTS
vii
5. FURTHER POSSIBILITIES OF FG DEVICE COMPACT MODELS 87 1.
RELIABILITY PREDICTI
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