Wafer Bonding Using Dielectric Polymer Thin Films in 3D Integration
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Wafer Bonding using Dielectric Polymer Thin Films in 3D Integration Y. Kwon, J.-Q. Lu, R. P. Kraft, J. F. McDonald, R. J. Gutmann and T. S. Cale Focus Center - New York, Rensselaer: Interconnections for Gigascale Integration Rensselaer Polytechnic Institute, Troy, New York 12180 ABSTRACT A key process in our approach to monolithic three-dimensional (3D) integration is the bonding of 200-mm wafers using dielectric polymer thin films as bonding glues. After discussing the desired properties of polymer thin films, we describe how bonding protocols are evaluated using silicon and glass wafers. After bonding, the fraction of bonded area was inspected optically and a razor blade method was used to indicate bonding strength. Thermal stability and bonding integrity were evaluated using thermal cycling and backside grinding and polishing. To date, we have studied benzocyclobutene (BCB), FlareTM, and methylsilsesquioxane (MSSQ) and Parylene-N as bonding glues. Wafer pairs bonded using BCB showed a larger fraction of bonded area, and those using Flare indicated higher thermal stability. Both BCB and Flare glues provided good bonding integrity after backside grinding tests. Changes in the chemical structures of BCB and Flare glue during bonding were analyzed using FTIR in order to understand the bonding mechanism and to improve the bonding process. INTRODUCTION Wafer bonding using dielectric polymer thin films as bonding glues is an important step in the process flow we use to fabricate three-dimensional (3D) ICs with active devices stacked in multiple layers. A schematic of 3D chip stacking using wafer bonding, thinning and inter-wafer interconnection is presented in Figure 1. Wafers stacked in this way can be fabricated with different unit processes and different wafer materials; hence, heterogeneous integration can be realized. This 3D technology may alleviate Cu/low-k interconnect bottlenecks and performance limitations of planar ICs caused by long wires [1]; i.e., interconnect delay can be reduced, and chip performance and functionality can be increased [1-4]. In addition, highly integrated systems may be realized using this 3D IC technology, e.g., hard intellectual property core-based implementations, and highspeed digital systems like application specific ICs or systems-on-a-chip [1,4]. For example, memory devices or image processing devices can be stacked with logic devices. In this paper we report on the silicon-to-glass wafer bonding using polymer thin films. Bonding studies on silicon and glass wafers are being used to evaluate proposed bonding protocols. The process technology developed in this work can be transferred to bonding of wafers made of other materials (e.g., silicon-to-silicon, SiO2-to-SiO2, siliconto-compound semiconductor). 3D IC STRUCTURE AND BONDING GLUE PROPERTIES Figure 2 shows an illustration of our 3D approach, which uses wafer bonding and copper damascene patterning for inter-wafer interconnection. Here, three wafers with ICs DD12.18.1
Wafers I/Os, A/Ds, sensors and glue logic Memory
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