Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration
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Planarization Issues in Wafer-Level Three-Dimensional (3D) Integration J.-Q. Lu, G. Rajagopalan, M. Gupta, T.S. Cale and R.J. Gutmann Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180, USA, [email protected] ABSTRACT Monolithic wafer-level three-dimensional (3D) ICs based upon bonding of processed wafers and die-to-wafer 3D ICs based upon bonding die to a host wafer require additional planarization considerations compared to conventional planar ICs and wafer-scale packaging. Various planarization issues are described, focusing on the more stringent technology requirements of monolithic wafer-level 3D ICs. The specific 3D IC technology approach considered here consists of wafer bonding with dielectric adhesives, a three-step thinning process of grinding, polishing and etching, and an inter-wafer interconnect process using copper damascene patterning. The use of a bonding adhesive to relax pre-bonding wafer planarization requirements is a key to process compatibility with standard IC processes. Minimizing edge chipping during wafer thinning requires understanding of the relationships between wafer bonding, thinning and pre-bonding IC processes. The advantage of silicon-on-insulator technology in alleviating planarization issues with wafer thinning for 3D ICs is described. INTRODUCTION While scaling of planar CMOS ICs combined with copper/low-k interconnect technology continues to drive productivity enhancements in integrated electronics, scaling beyond the 40 nm technology node is projected to be increasingly expensive and difficult [1]. Even the most innovative first-level single chip and multiple chip packaging approaches can limit IC performance capabilities and increase product cost. Wafer-level monolithic processing has the performance advantage of reduced interconnect parasitics and lower interconnectivity cost, thereby driving current interest in wafer-scale packaging (WSP) [2] and wafer-level three dimensional (3D) ICs. The latter also enable high density multifunctional integration (HDMI) or hyper-integration [3-5], and offers the potential for the highest volumetric density of integrated electronics and optoelectronics with a high density of high-performance, vertical interconnections. Various 3D technology platforms have been investigated, including hybrid dieto-wafer [6,7] and monolithic wafer-to-wafer approaches [3-5, 8-12]. Initial focus has been on different alignment strategies, bonding, thinning and inter-wafer (or inter-chip) interconnection approaches. However, wafer-level planarization requirements can be significantly different for the various 3D platforms. After a brief overview of viable 3D technology platforms, this paper focuses on comparison of wafer-level planarization needs for these platforms. Emphasis is placed on planarization issues associated with wafer bonding interface, wafer thinning, and damascene patterning of inter-wafer interconnects. Inter-wafer interconnect structu
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