3-D Integration Latest Developments at LETI
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0970-Y01-05
3-D Integration Latest Developments at LETI Barbara Charlet LETI/DIHS, CEA, 17, rue des Martyrs, Grenoble, 38054, France
ABSTRACT We review the latest 3-D integration developments performed in LETI, giving some device integration examples and discussing the achieved performance. Direct bonding and layer transfer (smart cut ™) is now largely used to process innovative substrates like: SOI, SSOI, GeOI … and others. This type of new substrate can play a crucial role in 3D structure integration and can answer the requirements for new challenging performances. 3-D integration approach has been used and will be presented in the following topics: advanced packaging by neo-wafers, chip-to-wafer integration, hetero-structures integration and wafer-towafer concept (front and back-end application). The examples of neo-wafer rebuilding for advanced packaging, the hetero- structure achieved by chip-to-wafer or wafer-to-wafer bonding and front-end and back-end architecture are discussed regarding the 3-D integration challenging requirements. The challenging cases of wafer-level integrated demonstrators for high density 3D inter-chips connections and wireless interconnections are presented. For some examples we give also the first electrical performances achieved with representative demonstrators. INTRODUCTION Advances in fundamental properties and technological approaches of thin materials give access to new concepts implemented to ICs and MEMS [1]. 3-D integration is one example, where multiple process schemes were developed using various innovative materials, processes and tools. Heterogeneous stacking of various materials or processed layers can be formed thanks to mature processes like: direct wafer bonding, bonding, bonding with intermediate layer, smart cut™ used for SOI, SSOI, GeOI. New concept equipment opportunities like precise alignment, efficient bonding or stacking, vias opening and filling – will contribute to the progress in various technological approaches for 3-D integration [2]. These progresses lead to 3-D structure achievements. Nowadays the first electrical test data and simulation models have demonstrated very promising performance such as: increase in speed and frequency and reduction of power consumption and dissipation. Furthermore new heterogeneous material integration can be achieved to obtain new functionalities. We review different approaches to 3D developed in collaboration with research institutes and industrial partners. A few examples of the 3D device integration and performance are discussed.
CHIP-TO-CHIP INTEGRATION Neo-wafers concept - developed with 3D Plus [3]. Integrated by standard FEOL and BEOL technology chips were again processed at the wafer level after the following steps: electrical testing, wafer backside thinning and dicing. The selection of the tested good dies and integration to the common support by an adhesive layer was done in order to supply the chips for interconnection rerouting on the consolidated wafer structure. Figure 1. depicts the main stages of the neo
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