A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics
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A Novel Low-Complexity and Energy-Efficient Ternary Full Adder in Nanoelectronics Seied Ali Hosseini1
· Sajjad Etezadi2
Received: 29 November 2019 / Revised: 5 August 2020 / Accepted: 10 August 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Using multi-valued logic can lead to reducing the interconnections in the chip. Reducing the interconnection, in turn, leads to decreasing the chip area and interconnections power dissipation. The design of the multi-valued logic circuits should be performed with the minimum complexity to fulfill the multi-valued logic aim. In the recent years, much research has been focused on the design of multi-valued logics in nanoelectronics due to the high capability of nanoelectronics to design them. In this paper, first, a novel single-supply ternary successor and predecessor are designed based on the multi-threshold voltage in CNFET, which is more energy efficient than those in the previous works. Then, these are used to design the ternary full adder. To reduce the number of transistors in the proposed full adder, the structure of this full adder is designed so that only one successor and predecessor are used and some common portions can be used in the sum and carry generator, and this is shown by equations. The number of transistors in the proposed single-supply full adder is reduced from 132 in the best previous single-supply full adder to 54. Also, to enhance the PDP, the successor and predecessor are used in the quad-state mode (‘0’, ‘1’, ‘2’ and ‘z’: high impedance), where in the ‘z’ mode, the direct current path is cut off. The circuits are simulated by the HSPICE software, using the Stanford 32 nm CNTFET library. The simulation results confirm the correct operation of the proposed circuit and PDP improvement in the proposed ternary full adder, which is about 81.12%, as compared to the best single supply reported in the previous works.
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Seied Ali Hosseini [email protected] Sajjad Etezadi [email protected]
1
Department of Electronic, College of Electrical Engineering, Yadegar-e-Imam Khomeini (RAH) Shahre Rey Branch, Islamic Azad University, Tehran, Iran
2
Department of Electronic, College of Electrical Engineering, Bandar Abbas Branch, Islamic Azad University, Bandar Abbas, Iran
Circuits, Systems, and Signal Processing
Keywords Multi-valued logic · Ternary logic · Successor · Predecessor · Ternary full adder
1 Introduction Multi-valued logics (MVL) are those with more than two logic levels [22]. Moreover, the ternary logic can be generated by adding one logic level to the binary logic. One of the main reasons for designing the multi-valued logic is the reduction of interconnections. This, in turn, leads to the reduction of the chip area and interconnections power consumption [12, 21, 26, 27]. A large part of the success of the MOS transistor is due to its scalability to much smaller dimensions, resulting in a better performance [1, 2, 4, 24, 38]. However, as MOSFETs are approaching their limiting size in the nanometer regim
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