A physics-based model for LER-induced threshold voltage variations in double-gate MOSFET
- PDF / 2,419,107 Bytes
- 9 Pages / 595.276 x 790.866 pts Page_size
- 108 Downloads / 165 Views
A physics‑based model for LER‑induced threshold voltage variations in double‑gate MOSFET S. R. Sriram1,2 · B. Bindu1
© Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract The line-edge roughness (LER) has become one of the dominant sources of process variations in multi-gate transistors. The estimation of threshold voltage distribution due to LER through atomistic simulations is computationally intensive, even though these simulations provide accurate results. In this paper, a physics-based model for channel LER-induced threshold voltage fluctuations due to variations of the silicon-body thickness in a double-gate (DG) MOSFET is presented. The developed VTH model gives more insights into the dependence of device and LER parameters on the VTH variations with a reduced computational time. The computed VTH variations due to different LER patterns are validated with TCAD simulations. The threshold voltage standard deviation due to LER in 500 device samples for different device dimensions, doping concentration and biases is studied. The developed model can be easily integrated in any circuit simulator to predict the threshold voltage variations of the devices due to LER. Keywords Double-gate MOSFET · Line-edge roughness (LER) · Potential model · Threshold voltage · Variability
1 Introduction The multi-gate MOSFET technology provides better control over the short channel effects and device scalability beyond the range of a bulk MOSFET [1]. However, the multi-gate transistor architecture increases the fabrication complexity and process defects leading to the characteristic mismatch between the adjacent transistors due to process variations such as random-dopant fluctuations (RDF) [2–4], lineedge roughness (LER) [5–7] and work function variation (WFV) [8]. The effect of random discrete dopants can be suppressed in multi-gate MOSFETs with the usage of lightly doped channel [9, 10] although the fluctuations of device dimensions due to line-edge roughness effects emerged as Manuscript received in September 2019. This work was supported by the Department of Science and Technology, Government of India, under Grant SERB/F/4194/2017-2018. * B. Bindu [email protected] 1
School of Electronics Engineering, Vellore Institute of Technology (VIT), Chennai, India
Department of Electronics and Communication Engineering, Easwari Engineering College, Chennai, India
2
one of the major sources of variability issues in multi-gate transistors. The amplitude of LER fluctuations is almost same and does not scale down with the scaling of technology [5]. The impact of gate LER due to variations of gate length increases with the scaling of the technology node in planar MOSFET [11]. Contrarily in multi-gate transistors, the impact of gate LER is much less than that of the channel LER due to variations of fin dimensions [6]. The channel LER is observed to be a leading concern among all the other variability issues in lightly doped double-gate FinFET [12]. The impact of channel LER in DG MOSFET, FinFET and tunn
Data Loading...
