Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET
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ORIGINAL PAPER
Interface Trap Charge Induced Threshold Voltage Modeling of WFE High-K SOI MOSFET Priyanka Saha 1
&
Pritha Banerjee 1 & Dinesh Kumar Dash 1 & Subir Kumar Sarkar 1
Received: 12 September 2019 / Accepted: 9 January 2020 # Springer Nature B.V. 2020
Abstract The present endeavor attempts to develop an explicit threshold voltage model of linearly graded work function engineered Silicon-On-Insulator MOSFET considering the effects of localized charges trapped at front high-k gate stack/channel and buried oxide layer/channel interfaces. As the accumulation of such equivalent oxide charges modulate the flat band voltage and alter the threshold voltage characteristics of the device, the inclusion of such effects is inexorable while formulating its analytical model. Hence, analytical methodology based extensive study of the potential distribution and threshold voltage behavior of the device affected by positive/negative trapped charges is demonstrated here by varying the channel thickness, high-k dielectrics and drain bias with subsequent comparison with a fresh SOI MOSFET equivalent. All analytical corollaries are compared with relevant ATLAS simulated data to corroborate the eminence of the derived model. Keywords SOI MOSFET . Binary metal alloy . Work-function engineered gate . Threshold voltage roll off . Positive/ negative trapped charges . High-k gate stack
1 Introduction The unhindered progress in the advancement of the microelectronics industries is only possible through device scaling that significantly contributes to meet the ever increasing technological demands of the modern era of civilization. Device miniaturization could have been a magical wand to achieve upgraded device performances but aggressive downscaling in nano-meter range poses vulnerable threats like the short channel effects (SCEs) [1] that tend to severely degrade the device performances. The conventional bulk MOSFETs when scaled down to nano-meter range are found to encounter major SCEs
* Priyanka Saha [email protected] Pritha Banerjee [email protected] Dinesh Kumar Dash [email protected] Subir Kumar Sarkar [email protected] 1
Department of Electronics and Telecommunication Engineering, Jadavpur University, Kolkata 700032, India
like threshold-voltage roll-off (TVRO), drain-induced barrier lowering (DIBL), subthreshold slope degradation, etc. [2]. This paved the path for the introduction followed by suitable implementation of the avant-garde technologies in the existing MOSFETs thereby aiming to achieve groundbreaking advanced MOSFET structures with improved device features. One of such technologies is the application of gate work function engineering where the gate is made of more than one material, such as dual-material gate, triple material gate etc. [3, 4]. A pioneering scheme of gate work function engineering is the linearly graded binary metal alloy gate that comprises of binary metal alloy (KxL1-x) with work function laterally varying from source (100% K) to drain end (100% L). This continuous variati
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