Calculating Threshold Voltage Shift for Shallow Implanted Short-Channel MOSFET in Presence of High-K Dielectric
Shift of threshold voltage is analytically measured for shallow implanted short-channel MOSFET considering HfO2 as dielectric material. With suitable design parameters, depletion width is made greater than implant depth, and Poisson’s equation is solved f
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Abstract Shift of threshold voltage is analytically measured for shallow implanted short-channel MOSFET considering HfO2 as dielectric material. With suitable design parameters, depletion width is made greater than implant depth, and Poisson’s equation is solved for threshold voltage computation under inversion condition. Simulated findings are compared with the ideal results obtained for sheet charge approximations and for different structural and doping parameters. For every design consideration, corresponding implant depth is also computed as a function of substrate ion concentration. Results are important for design of transistors under such doping condition in the submicron region. Keywords Threshold voltage shift · Shallow implant · Implant depth · Depletion width · High-K dielectric
1 Introduction In present day, ion implantation processed is favored for fabrication of lowdimensional devices [1, 2]; but with the shrinking in the dimension of devices [3], problems related to transistors falsely trigger themselves with unwanted/noise signals at the gate terminal. Many different techniques have been applied [4, 5] to prohibit the undesired behavior of the transistors when incorporated in the VLSI circuit. In present VLSI systems, local oxidation of silicon process (LOCOS) is being applied, but for the future processes like the ULSI or the GLSI where the dimension is less R. Dhar · A. Deyasi (B) Department of Electronics and Comm Engineering, RCC Institute of Information Technology, Kolkata, India e-mail: [email protected] R. Dhar e-mail: [email protected] P. Halder Department of Electronics and Comm Engineering, Dream Institute of Technology, Kolkata, India © The Editor(s) (if applicable) and The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2021 V. Nath and J. K. Mandal (eds.), Proceedings of the Fourth International Conference on Microelectronics, Computing and Communication Systems, Lecture Notes in Electrical Engineering 673, https://doi.org/10.1007/978-981-15-5546-6_37
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than 1 µm, LOCOS technique is not going to work satisfactorily [6]. Therefore, the need of novel techniques becomes the need of the hour [7, 8]. The trench isolation process is one of those processes already reported in various literatures [9, 10] which can satisfactorily overcome this problem so far. For isolation of very high-voltage devices at the terminals/junctions, we have to create larger separation between two consecutive devices, which is impractical from the miniaturization of chip size point of view. In this context, the use of deep trench isolation [11, 12] significantly reduces the device size, hence reducing the device cost. Even though transistors are isolated in a circuitry by a deep trench structure, they start to become connecting between themselves by virtue of inter-capacitance property and thus greatly degrade the electrical performance of the circuit. The quality of the trench sidewall (i.e., the silicon/trench interface) is also extremely crucial i
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