Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs
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Bias Temperature Instability (BTI) in high-mobility channel devices with high-k dielectric stacks: SiGe, Ge, and InGaAs (Invited Paper) J. Franco1, B. Kaczer1, A. Vais1,2, A. Alian1, H. Arimura1, V. Putcha1,2, S. Sioncke1, N. Waldron1, D. Zhou1, L. Nyns1, J. Mitard1, L. Witters1, M. Heyns1,2, G. Groeseneken1,2, N. Collaert1, D. Linten1, A. Thean1 1
imec, Kapeldreef 75, 3001 Leuven, Belgium
2
KU Leuven, Belgium
ABSTRACT We present a review of our recent studies of Bias Temperature Instability (BTI) in MetalOxide-Semiconductor Field-Effect-Transistors (MOSFETs) fabricated with different material systems, highlighting the reliability opportunities and challenges of each novel device family. We discuss first the intrinsic reliability improvement offered by SiGe and Ge p-channel technologies, if a Si cap is used to passivate the channel, in order to fabricate a standard SiO2/HfO2 gate stack. We focus on SiGe gate stack optimizations for maximum BTI reliability, and on a simple physics-based model able to reproduce the experimental trends. This model framework is then used to understand the suboptimal BTI reliability and excessive timedependent variability induced by oxide defect charging in different high-mobility channel gate stacks, such as Ge/GeOx/high-k and InGaAs/high-k. Finally we discuss how to pursue a reduction of charge trapping in alternative material systems in order to boost the device reliability and minimize time-dependent variability. INTRODUCTION Reliability and variability are becoming showstoppers for further scaled CMOS technology nodes [1,2]. The traditional 10 year reliable operation cannot be guaranteed anymore at the single device level, mainly due to severe Bias Temperature Instability (BTI) [3] inducing both degradation of the average device electrical properties (threshold voltage, Vth, subthreshold swing, SS, transconductance, gm, and ultimately the drive current) by oxide defect charging and interface state generation, and additional device-to-device variability [4], particularly when highk gate stacks are used. Meanwhile, the combination of finFET architectures with high-mobility channel materials [5] is emerging as the frontrunner option to maintain the established pace of performance enhancement in future technology nodes, posing new questions about device and material reliability. Here we review our studies of BTI in SiGe and Ge devices with SiO2 interfacial layer (IL) obtained by oxidation of an epitaxially grown Si cap [Fig. 1 (a)], Ge devices with GeOx IL (fabricated by thermal or plasma enhanced oxidation, [Fig. 1 (b)] and InGaAs devices with Al2O3 gate dielectric [Fig. 1 (c)], highlighting the reliability opportunities and challenges of each device family.
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p- and n-channel FETs
(a) p-channel FET
(b)
TiN HfO2
SiO2
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