Investigations on the Logic Circuit Behaviour of Hybrid CMOSFETs Comprising InGaAs nMOS and Ge pMOS Devices with Barrier
We investigate the logic circuit behaviour of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length L g = 20 and 30 nm. Rise and fall time, noise margin of hybrid CMOS invert
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Abstract We investigate the logic circuit behaviour of hybrid CMOS devices made of InGaAs n-channel and Ge p-channel MOSFETs with Si and InP barrier layers, respectively, at channel length Lg = 20 and 30 nm. Rise and fall time, noise margin of hybrid CMOS inverters and frequency of oscillations, energy-delay product of 3-stage ring oscillators comprising hybrid CMOS inverters have been investigated to evaluate the performance of the proposed CMOS device. Our findings show a significant amount of reduction of 92.2 and 82.5% for rise and fall time, respectively, in case of proposed hybrid inverter, compared with the corresponding values for equivalent Si CMOS at Lg = 30 nm. Oscillation frequency of a 3-stage ring oscillator is found to be 264% higher when compared with its Si counterpart. Also there is an improvement of 17.8 and 77.4% in power-delay and energy-delay product, respectively, for hybrid CMOS inverters in comparison with their equivalent Si counterparts for a channel length of 30 nm. Similar trend is observed in case of channel length of 20 nm.
Keywords Hybrid CMOS Logic performance Noise margin Rise time Fall time Frequency of oscillations
1 Introduction To continue the historical performance improvement of complementary metal-oxide semiconductor (CMOS) devices for logic circuit applications beyond 32 nm channel length, the CMOS device made up of a p-Ge and n-InGaAs S. Tewari A. Biswas (&) Department of Radio Physics and Electronics, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata 700009, India e-mail: [email protected] A. Mallik Department of Electronic Science, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata 700009, India © Springer Nature Singapore Pte Ltd. 2018 V. Nath (ed.), Proceedings of the International Conference on Microelectronics, Computing & Communication Systems, Lecture Notes in Electrical Engineering 453, https://doi.org/10.1007/978-981-10-5565-2_13
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MOSFETs has become a promising alternative to Si counterpart [1–8]. The choice of InGaAs channel is due to its outstanding electron transport properties such as mobility and injection velocity, while Ge is chosen owing to its record high hole mobility. Use of a barrier layer such as InP for InGaAs channel and a Si barrier for Ge channel confines carriers in the channel and improves carrier mobility further. Several reports have been published in which the integration of a p-Ge and n-InGaAs MOSFETs was demonstrated to form the CMOS device on a common Si platform [9]. The task of co-integration of InGaAs nMOS and Ge pMOS on a common platform of Si offers various challenges; however, Takagi et al. have recently reported fabrication of both the devices on the same Si platform using direct wafer bonding technique [9]. Wang et al. have already reported in ref. [10] the direct growth of III–V and Ge in STI trenches of Si adopting aspect ratio trapping. Additionally, CMOS circuits comprising InGaAs nMOS and Ge pMOS devices, using the same gate stack, as demonstrated
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