CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process
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CMP Compatibility of Partially Cured Benzocyclobutene (BCB) for a Via-First 3D IC Process J. J. McMahon, F. Niklaus, R. J. Kumar, J. Yu, J.-Q. Lu, and R. J. Gutmann Focus Center-New York, Rensselaer: Interconnections for Hyperintegration Center for Integrated Electronics Rensselaer Polytechnic Institute, Troy, New York-12180 ABSTRACT Wafer-level three dimensional (3D) IC technology offers the promise of decreasing RC delays by reducing long interconnect lines in high performance ICs. This paper focuses on a viafirst 3D IC platform, which utilizes a back-end-of-line (BEOL) compatible damascene-patterned layer of copper and Benzocyclobutene (BCB). This damascene-patterned copper/BCB serves as a redistribution layer between two fully fabricated wafer sets of ICs and offers the potential of high bonding strength and low contact resistance for inter-wafer interconnects between the wafer pair. The process would thus combine the electrical advantages of 3D technology using Cu-toCu bonding with the mechanical advantages of 3D technology using BCB-to-BCB bonding. In this work, partially cured BCB has been evaluated for copper damascene patterning using commercially available CMP slurries as a key process step for a via-first 3D process flow. BCB is spin-cast on 200 mm wafers and cured at temperatures ranging from 190oC to 250oC, providing a wide range of crosslink percentage. These films are evaluated for CMP removal rate, surface damage (surface scratching and embedded abrasives), and planarity with commercially available copper CMP slurries. Under baseline process parameters, erosion, and roughness changes are presented for single-level damascene test patterns. After wafers are bonded under controlled temperature and pressure, the bonding interface is inspected optically using glass-to-silicon bonded wafers, and the bond strength is evaluated by a razor blade test. INTRODUCTION As technology challenges and costs increase for scaling, 3D integration is becoming an attractive option for driving the performance enhancement of current ICs. Presently, 3D integration provides attractive small form factor solutions and heterogeneous integration for mobile device applications through die stacking [1]. However, wafer-level 3D interconnect technology offers this capability coupled with the manufacturing advantages of batch fabrication, and is a strong candidate to reduce future RC delays by shortening long interconnect lines [2]. Wafer-level 3D technologies have been demonstrated and differ in fabrication methods, material sets, and ease of integration within current IC fabrication process flows. A key enabling processing step is back-end-of-line (BEOL) compatible wafer bonding, including three approaches: silicon dioxide (SiO2) bonding, copper bonding, and adhesive bonding. In the SiO2 bonding approach, wafers are bonded at a low temperature with atomically smooth surfaces [34]. The copper-to-copper bonding approach utilizes raised copper landing pads to provide mechanical bonding integrity as well as electrical interconnec
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