Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications
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ORIGINAL PAPER
Core-Shell Nanowire Junctionless Accumalation Mode Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications - Analytical Study Sonam Rewari 1 Received: 9 September 2020 / Accepted: 28 September 2020 # Springer Nature B.V. 2020
Abstract Here, an analytical model has been proposed for Core-Shell-Nanowire-Junctionless-Accumulation-Mode- Field-Effect Transistor (CSN-JAM-FET) for High Frequency Applications. CSN-JAM-FET has been contrasted with NanowireJunctionless- Accumulation- Mode- Field-Effect Transistor (NJAM-FET) under the similar device conditions by keeping the threshold voltage same for both. It is so found that CSN-JAM-FET shows much higher drain current (Ids), transconductance (gm), output conductance (gd), Ion/Ioff ratio, Subthreshold Slope (SS) and cut off frequency (fT) because of the inherent property of core shell architecture to elevate the gate domination over the channel. The analytical results have also been modelled for CSN-JAMFET by finding a result of the Two-Dimensional Poisson equation in accordance with the boundary conditions. The analytical results are much in coherence with the results obtained from the simulator. Keywords Core-Shell . Junctionless Accumulation Mode . Nanowire . Analog
1 Introduction An incredible change is observed in the semiconductor commerce and the evolution still remains never ending and the device length is being constantly reduced for Ultra Large Scale Integrations (ULSI) [1]. Even in sub-0.1 μm many SCEs, which deeply the overall scalability of the device, such as increment in the subthreshold slope (SS), which demands consideration [2]. Potential of silicon technologies beyond 100 nm regime has been well indicated by modeling and simulation [3–5]. To combat the effects of SCEs, many variants of device designs have been recommended and deeply studied by the researchers. The Gate All Around (GAA)/ Nano. Wire (NW) structures had been the most encouraging device structure for MOSFETs beyond 10 nm regime [6–11]. Nonetheless, the NW device structures require to be stacked into arrays to excerpt an agreeable drive current, so that the chip area is exhausted appreciably opposing the benefits of scaling. The exploration of FET structures for an improvised * Sonam Rewari [email protected] 1
Department of Electronics and Communication Engineering, Delhi Technical University, New Delhi 110042, India
output drive current from the three-dimensional topologies, has led to the coinage of silicon Nano-Tube (NT) with core gate structure. Nanotube / Core-Shell architecture is being investigated these days which combats the SCE’s of GAA/ Nanowire MOSFETs [12–18]. This superior gate control also administers exquisite amnesty towards the SCEs and a competent volume inversion, leading to high drive currents in addition to the impressive employment of the real-estate [14, 15, 19].This architecture provides a superlative gate control as compared to all its counterpart NW device architectures [12–17]. Technically, lately proposed Junctionless (JL) MOSFE
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