Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines
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0914-F08-01
Effects of BEOL Stack on Thermal Mechanical Stress of Cu Lines Seung-Hyun Rhee1, Conal E. Murray2, and Paul R. Besser2,3 1 Logic Technology Development, Advanced Micro Devices, Fishkill, NY, 12533 2 T.J. Watson Laboratory, IBM Research Division, Yorktown Heights, NY, 10598 3 Technology Research Group, Advanced Micro Devices, Sunnyvale, CA, 94088 ABSTRACT The measurement and control of the stress state in BEOL interconnects are important to ensure structural integrity and long term reliability of integrated circuits. Thermal stress in interconnects is determined by the thermalmechanical properties of Cu lines, substrate, and dielectric materials. The effect of BEOL stacks on thermal stress characteristics of Cu lines were investigated using X-ray diffraction stress measurements. The stress characteristics of M1 and M4 level interconnects in full low-k and low-k/oxide hybrid dielectric stacks were evaluated, and the results indicated reduced substrate confinement and an increased impact of the dielectric material on in-plane stresses in higher level interconnects. The effects of dielectric stack and material properties were examined and the implication in the stresses of multilevel interconnects are discussed. INTRODUCTION The back-end-of-line (BEOL) interconnect structure consists of several different materials including metal, dielectric, diffusion barrier, and capping layer on top of a thick Si substrate. The fabrication of the structure usually accompanies several thermal cycles from room temperature up to at least 400oC depending on the process, and large stresses can be introduced due to thermal expansion mismatch among these materials. The buildup of large stresses in thin interconnect lines can be a major reliability concern. Large compressive stresses can cause the formation of hillocks in the metal lines. The existence of large tensile stresses, on the other hand, act as a driving force for several stress relaxation mechanisms including stress induced void formation in the interconnect lines. The presence of large shear stresses can introduce volumeconserving plastic deformation in the interconnects. In addition, large stresses may also cause other reliability problems such as failure of the metal/dielectric interfaces. During the past few years, the microelectronics industry has aggressively implemented low dielectric constant (low-k) materials as inter-layer dielectrics (ILDs) to reduce RC delay in interconnects. Low-k dielectric materials usually possess orders of magnitude larger coefficients of thermal expansion (CTE) and much weaker mechanical properties compared to traditional oxide materials. These differences in material properties lead to different thermal stress behavior in Cu interconnects, and the stress characteristics need to be properly evaluated
and controlled in order to ensure thermal-mechanical stability, structural integrity and long-term stress reliability. Thermal stresses in Cu interconnects with oxide or low-k dielectrics have been widely studied both experimentally an
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