Effects of Channel Dimension and Doping Concentration of Source and Drain Contacts on GNRFET Performance
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ORIGINAL PAPER
Effects of Channel Dimension and Doping Concentration of Source and Drain Contacts on GNRFET Performance Tahereh Radsar 1 & Hassan Khalesi 1
&
Vahid Ghods 2 & Alireza Izadbakhsh 1
Received: 21 February 2020 / Accepted: 15 September 2020 # Springer Nature B.V. 2020
Abstract Growth of the electronic industry has been accompanied by the increasing number of components on a chip. Consequently, it is necessary to shrink device dimension. In this paper, effects of channel dimension reducing of the graphene nanoribbon field effect transistors (GNRFET) on performance of the GNRFET are studied. Also, effects of increasing in source/drain contacts doping concentration of the GNRFET are discussed. In order to device simulation, non-equilibrium Green’s function (NEGF) equation is applied for self-consistent solving of Poisson and Schrödinger equations with the tight binding approximation in the mode space and ballistic regime. According to the simulation results, channel length reduction of the GNRFET causes higher values in ON-state and OFF-state currents, transconductance (gm), subthreshold swing and drain induced barrier lowering (DIBL). Also, it causes lower values in threshold voltage and ION/IOFF ratio. Decreasing in channel width of the GNRFET, causes lower values in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes higher values in ION/ IOFF ratio and threshold voltage. Increasing in source/drain contacts doping concentration of the GNRFET causes increasing in ON-state and OFF-state currents, DIBL, subthreshold swing and gm. Also, it causes decreasing in ION/IOFF ratio and threshold voltage. The effects of channel dimension reducing and contacts doping concentration on the transistor performance should be considered for optimal design, fabrication and selection of GNRFETs in various circuits and applications. Keywords Graphene nanoribbon field effect transistor . GNRFET . ION/IOFF ratio . Drain induced barrier lowering . Subthreshold swing
1 Introduction The scalability of the silicon based transistors has been main reason for improvement in performance of the integrated circuits and devices. As a result, great development in the
* Hassan Khalesi [email protected] Tahereh Radsar [email protected] Vahid Ghods [email protected] Alireza Izadbakhsh [email protected] 1
Department of Electronic Engineering, Garmsar Branch, Islamic Azad University, Garmsar, Iran
2
Department of Electronic Engineering, Semnan Branch, Islamic Azad University, Semnan, Iran
electronics industry was generated. Because of the dimension reduction of the transistors, fundamental problems, challenges and limitations are produced with the devices manufacturing and operation. Some of them are short channel effects, power dissipation, changes in manufacturing processes and increasing in production costs [1–3]. Moore law declared the number of the transistors in an integrated circuit have been doubled every 18 month, this means that the dimension of the device
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