Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness
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ORIGINAL PAPER
Enhancement of Performance in TFET by Reducing High-K Dielectric Length and Drain Electrode Thickness C. Sheeja Herobin Rani 1 & K. Bhoopathy Bagan 2 & D. Nirmal 3 & R. Solomon Roach 4 Received: 23 July 2019 / Accepted: 13 November 2019 # Springer Nature B.V. 2019
Abstract A Dual Material Double Gate Tunnel Field Effect Transistor (DMDGTFET) with reduced high-K dielectric length (LK = 15 nm) and drain electrode thickness (6 nm) is proposed and performed a TCAD simulation. The simulation result of proposed device exhibits suppression in gate-to-drain capacitance (CGD). The (CGD) is proportional to dielectric constant (ε) of the gate insulator and drain-electrode thickness of device. In the proposed DMDGTFET, the reduction in drain electrode thickness and LK gives a low electron concentration (Q) and low dielectric constant (ε) in channel/drain junction, respectively, which results in suppression of CGD. At VGS = 2 V, the CGD for the proposed and conventional device are 9 f F, and 7 f F, respectively. In addition, the proposed device exhibit unity current-gain cut-off frequency of 62 GHz, while it is 57 GHz for conventional device. The oncurrent (ION) of the proposed device is also measured as 2 × 10−5 (A/mm). Thus, the proposed DMDGTFET is potential candidate for fast switching applications without compromising on-current (ION). Keywords Triple material double gate tunnel field effect transistor (TMDG TFET) . Surface potential . Electric field . Poisson’s equation . Band-to-band tunneling (BTBT)
1 Introduction In low power as well as high power applications, MOSFET proved it as an excellent device in the semiconductor industry for several decades [1–7]. For low power application, the size * C. Sheeja Herobin Rani [email protected] K. Bhoopathy Bagan [email protected] D. Nirmal [email protected] R. Solomon Roach [email protected] 1
Department of ECE, St. Xavier′s Catholic College of Engineering, Chunkankadai, Tamil Nadu, India
2
Department of Electronics Engineering, Madras Institute of Technology, Chennai, Tamil Nadu, India
3
Department of ECE, Karunya Institute of Technology and Sciences, Coimbatore, India
4
ASIC Engineer, Test and Verification Solutions India Pvt. Limited, Chennai, India
of the MOSFET is aggressively scaled down by continuous effort. The power consumption is reduced by scaling down the size of the MOSFET. At room temperature, the subthreshold swing of TFET devices are lower than 60 mv/decade compared to conventional MOSFETs this inturn increases the switching speed of TFET. The short channel effect does not occur in TFET since the carrier transport is based on tunneling mechanism, while the carrier transport in MOSFET is based on thermionic emission. The tunneling mechanism is also an attractive feature of TFET since it exhibit lower sub-threshold swing (SS). In addition to these features of TFET, a lot of technological advancement has been made in TFET in the last few decades which are given as follows. The improvement in sub-threshold swing (SS) and on-current w
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