Experimental and theoretical investigation of bifurcated wafer warpage evolution in the wafer level packaging processes
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Experimental and theoretical investigation of bifurcated wafer warpage evolution in the wafer level packaging processes Chunsheng Zhu1 Received: 24 May 2020 / Accepted: 7 August 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Wafer warpage, which mainly originated from thermal mismatch between the materials, has become serious in wafer level packaging (WLP) as larger diameter and thinner wafers are required currently. In this paper, three-dimensional wafer warpage profile and the warpage evolution during typical fan-in WLP processes including wafer thinning process were characterized in situ. Special attention was paid to the bifurcated phenomenon. Prior to the wafer thinning process, the wafer deformed into a bowl shape which was caused by polyimide (PI) curing. A distinct bifurcation behavior appeared and the wafer warped into a cylindrical shape when the wafer was thinned below 270 μm. This bifurcation behavior was systematically analyzed by theoretical analysis and finite element analysis (FEA). Equivalent material model method and perturbation method were employed to simplify the FEA model and incur the bifurcation behavior, respectively.
1 Introduction Wafer level package (WLP) has gained tremendous attention in semiconductor packaging field for its prominent advantages in small packaging size, better electrical and thermal performance, batch production, and low cost [1, 2]. Among the various WLP technologies, fan-in WLP is extensively used in applications such as analog, power, mixed signal, opto, MEMS, and sensors [3, 4]. Fan-in WLP is also known as wafer level chip scale package (WLCSP) precisely because it provides truly chip scale package size and allows chips to be flip bonded to printed circuit board (PCB) without underfill [5, 6]. Redistribution layer (RDL) and solder bumping are two important technologies in WLCSP, which are shown in Fig. 1. RDL is a combination of polymer dielectric and metal layers and is designed to re-route the peripheral pads layout into a solderable planar pad array. In RDL, polyimide (PI) or polybenzoxazole (PBO) is often employed as the dielectric material and Cu is the primary choice of the metallization material for its low interconnect resistance [7]. To achieve WLCSP, several thermal processes should be carried out. For example, wafer will undergo a typical * Chunsheng Zhu [email protected] 1
Strategic Support Force Information Engineering University, Zhengzhou 450001, China
375 °C thermal process to cure the PI dielectric layer. Since considerable coefficient of thermal expansion (CTE) differences exist among the PI, Cu, solder bump and silicon wafer, thermal stresses will be accumulated and wafer warpage will be induced after the thermal processes. Wafer warpage, which is defined as the out-of-plane deformation, is one of the major reliability concerns in WLP technology. With the development of smaller and thinner mobile products, it stimulates the need for thinner wafers to decrease the package thickness. However, a slightly war
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