Through Wafer Interconnects for 3-D Packaging
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0970-Y01-06
Through Wafer Interconnects for 3-D Packaging Amy J. Moll1, William B. Knowlton2, and Rex Oxford2 1 Materials Science & Engineering, Boise State University, 1910 Univ Dr, Boise, ID, 83725-2075 2 Materials Science & Engineering, Boise State University, Boise, ID, 83725-2075 ABSTRACT Semiconductor technology has reached a point in its evolution where the package now plays an important role in the overall performance of the device. In MEMs devices, the package is often more than 75% of the cost and has a significant impact in the overall size. Through wafer interconnects allow for advanced 3-D packaging schemes. Additional miniaturization, increased interconnection density, and higher performance is possible by stacking die with through wafer interconnects. Key technologies for creating TWIs are the ability to create a via through the silicon wafer, dielectric isolation of the via metal from the substrate, and filling or coating the via with a conducting material. Through wafer interconnects have been demonstrated in silicon wafers. The process to create TWIs has been optimized. The TWI has been tested electrically and proven reliable. TWIs were incorporated into an active device wafer and a two die stack connected through solder bump technology. In current work, specific applications which take advantage of the benefits of TWI’s are being explored including 3-D inductors, unique sensor packages and MEMs applications. INTRODUCTION Demand for small and portable electronics has resulted in the development of smaller, higher density integrated circuits (ICs) to be used in next generation micro-electronics [1,2]. Die stacking is one method to further miniaturize electronic devices while increasing functionality. New packaging methods such as system-in-a-package (SiP), chip-scale-packaging (CSP) and vertical die stacking (3-D) are just a few examples of novel packaging schemes used to minimize chip real estate. Other methods explored have included folded packages, chips imbedded in a polymer material and die-side metal contacts [3,4]. Although new methods are being used to shrink die footprints, wire bonding still remains as a common method used to create interconnects between stacked layers. With die stacked configurations, however, the number of I/Os is increased creating problems with reliability due to the complexity of wire bond routing paths. System performance can also be degraded due to increased interference susceptibility and the propensity for increased RC delay. One alternative solution for creating decreasing the interconnect complexity in 3-D die stacking configurations is through the use of copper through wafer interconnects (TWIs). Copper through-wafer interconnects are small copper filled vias formed through the die which act as the electric communication pathways between stacked layers. TWIs have been shown to provide dramatic improvements in chip performance including increased speed, decreased propagation delay and lower power requirements [5]. Shown in Figure 1 is just one example of a typi
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