Modeling the Characteristics of SOI CMOS Nanotransistors with an Asymmetric Surrounding Gate
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ling the Characteristics of SOI CMOS Nanotransistors with an Asymmetric Surrounding Gate N. V. Masal’skii* Federal State Institution “Scientific Research Institute for System Analysis,” Russian Academy of Sciences, Moscow, 117218 Russia *e-mail: [email protected] Received February 5, 2020; revised March 19, 2020; accepted March 19, 2020
Abstract—An approach to an end-to-end simulation of the electrophysical characteristics of lowly doped sub25-nm SOI (silicon-on-insulator) CMOS transistors with an asymmetric surrounding gate composed of two sequentially connected materials with different work functions is considered. The approach consists of the consecutive calculation of the 3D potential distribution in the working region, calculation of the current– voltage characteristics, and calculation of the static and dynamic characteristics for a basic logic gate (an inverter). In the context of the discussed approach, the effect of the ratio between the lengths of the gate regions with different work functions on all the key characteristics of the devices (transistors and logic gates based on them) are analyzed. It is demonstrated that the logic gates can operate efficiently at a supply voltage of 0.8 V, which is a prerequisite for the creation of low-voltage circuit engineering. Keywords: SOI CMOS nanotransistor, asymmetric gate, 3D potential distribution, current–voltage characteristics, inverter, low supply voltage DOI: 10.1134/S1063739720050066
INTRODUCTION Further improvement in the efficiency of silicon integrated circuits is directly connected with the use of new transistor architectures [1, 2]. In the present work, to tackle the highlighted issue, the possibility of using SOI (silicon-on-insulator) CMOS nanotransistors with an asymmetric surrounding gate is analyzed [1–4]. In the considered structure, the gate is composed of two sequentially connected materials M1 and M2 with different work functions. In such a configuration, due to the spike of the surface potential, the electric field’s peak at the drain decreases greatly, which makes it possible to suppress both the short-channel effects (SCEs) and decrease the hot carriers’ effect [5–8]. The advantage of this design is the opportunity to compensate the roll-off effect of the threshold voltage and other spurious mechanisms. Such a concept is tested with several planar architectures. The efficiency of such a design is appreciable for lowly doped working regions [9]. When the net number of carriers is large, the spike in the potential is insufficient for the efficient suppression of the hot carriers’ effect [5, 8]. Investigation of the possibility of applying the concept of a combined gate for the surrounding gate transistor structures is of interest due to their superiority (in terms of speed of operation, power consumption, and miniaturization) over the properties of analogous planar structures [2, 10].
A functional schematic of an SOI CMOS dualmaterial surrounding gate nanotransistor is shown in Fig. 1. In this case, the following elements are located on an
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