Silicides for the 65 nm Technology Node
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Silicides for the 65 nm Technology Node Paul R. Besser, Simon Chan,* Eric Paton, Thorsten Kammler,# David Brown,@ Paul King,* and Laura Pressley & Technology Development Group, Advanced Micro Devices, Inc. One AMD Place, Mail stop 36, Sunnyvale, CA 94087 USA *FASL LLC, Advanced Micro Devices, Sunnyvale, CA # AMD Saxony LLC & Co KG, Dresden, Germany @ Advanced Micro Devices, East Fishkill, NY & FASL LLC, Advanced Micro Devices, Austin, TX ABSTRACT At the 65 nm node, silicide faces formidable challenges. Co is the current process of record for most integrated circuit manufacturers and thus becomes baseline silicide for 65 nm. However, Ni is the likely replacement. Both silicides are challenged to meet the requirements at the 65 nm node. This manuscript reviews the current CoSi2 challenges (dopant interactions, Ge interactions, linewidth extendibility, impurity effects, agglomeration issues, etc). Ni consumes less Si but has its own challenges, including issues with contact leakage and thermal budget, excessive diffusion and oxidation, interactions with dopant and impurities. Both silicides have formation and stability issues in the presence of Ge. Additions of Ge increase the temperature at which a low resistance CoSi2 is formed due to film segregation into CoSi2 and Ge-rich Si-Ge grains. With Ni, additions of Ge decrease the temperature at which NiSi converts to a NiSi2, lead to agglomeration at a lower temperature and lead to germanosilicide formation. CHALLENGES FOR SILICIDES AT THE 65 NM NODE One of the key challenges for future CMOS technologies is the formation of low-resistance, shallow junctions. Silicide is an integral element for shallow junctions, and cobalt silicide is the silicide of choice for most IC manufacturers. Cobalt silicide (CoSi2) replaced titanium silicide (TiSi2) at the 250 nm technology node[1-4] and has been used for the 180, 130 and 90 nm technology nodes. While Co has some challenges, such as the need for a capping layer[2-13] and a sensitivity to impurities,[10-13] CoSi2 advantageously eliminates the linewidth-dependent sheet resistance exhibited by TiSi2,[1] provides a low resistivity material on active and polysilicon, and provides a low resistance contact to the Si device, enabling higher performance microprocessors. At the 65 nm technology node, CoSi2 faces formidable challenges created by the anticipated technology changes. These technology changes are best described by the International Technology Roadmap for Semiconductors [14] and are highlighted in Table 1. With gate dimensions expected to reduce to 25 nm (and smaller), the most daunting challenge may be the aggressive shrinking of the poly gate width. In order to enable shallow junctions and ultra thin Si associated with SOI substrates, the silicide must be thin and not consume too much Si. The contact resistance between the silicide and the active Si must be low and the level of dopants will be high. Additionally, a host of materials changes may occur at the 65 nm node, including highK gate dielectrics, selective epita
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