Silicides for 65 nm CMOS and Beyond
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Silicides for 65 nm CMOS and Beyond Jorge A. Kittl1, Anne Lauwers, Oxana Chamirian, Mark Van Dal2, Amal Akheyar3, Olivier Richard, Judit G. Lisoni, Muriel De Potter, Richard Lindsay and Karen Maex IMEC, Kapeldreef 75, 3001 Leuven, Belgium 1 Affiliate researcher at IMEC from Texas Instruments 2 Philips Research Leuven, Kapeldreef 75, 3001 Leuven, Belgium 3 Affiliate researcher at IMEC from Infineon Technologies ABSTRACT An overview of silicide development for the 65 nm node and beyond is presented. The scaling behavior of Co based and Ni based silicides to sub-100 nm junctions and sub-40 nm gate lengths was investigated. Co and Co-Ni silicides required a high thermal budget to achieve low diode leakage. Even for lower thermal budgets, the sheet resistance of Co and Co-Ni silicides increased at gate lengths below 40 nm. NiSi had low sheet resistance down to 30 nm gate lengths exhibiting a reverse linewidth effect (sheet resistance decreased with decreasing linewidth), achieved lower contact resistivity than CoSi2 and lower diode leakage for similar sheet resistance values. Bridging issues cannot be ignored for NiSi, in particular for thicker Ni films, higher RTP temperatures and in the presence of Ti. Material issues for the application of NiSi were also investigated. Ni2Si was found to grow with diffusion limited kinetics in the 225-300oC range, with an activation energy of 1.5 eV. Results of the kinetic studies were used to design a two-step RTP process that limited the silicide thickness on small features by a low thermal budget first RTP step, reducing the reverse linewidth effect and avoiding excessive silicidation. In the presence of an interfacial oxide, undesired epitaxial NiSi2 pyramidal grains grew directly at temperatures as low as 310oC on p+ Si. Thermal stability of NiSi was also investigated. We found that the initial mechanism of degradation for thin NiSi films was agglomeration, with activation energies of 2.5-3 eV. The surface after agglomeration remained quite flat with alternating NiSi and exposed Si areas, while the interface roughened significantly. Thick films also degraded initially by agglomeration at low temperatures, but by transformation to NiSi2 at higher temperatures. The addition of Pt improved thermal stability of NiSi films against agglomeration. The Ni/Si-Ge reaction was also studied, finding that the addition of Ge reduced the thermal process window and resulted in a slightly higher resistivity. INTRODUCTION Self-aligned silicide (SALICIDE) processes are used in complementary metal-oxide semiconductor (CMOS) flows to reduce sheet resistance and provide low contact resistivity on gate, source and drain areas. Several considerations need to be taken into account when designing a SALICIDE process (figure 1). Co silicide [1-5] replaced Ti silicide as the mainstream silicide used in CMOS technologies and is currently widely used in production at the 130 nm node. However, SALICIDE processes face difficult challenges as CMOS technologies are scaled to gate lengths below 40 nm and jun
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