Issues and Optimization of Millisecond Anneal Process for 45 nm Node and Beyond
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0912-C04-06
Issues and Optimization of Millisecond Anneal Process for 45 nm Node and Beyond Kanna Adachi1, Kazuya Ohuchi1, Nobutoshi Aoki1, Hideji Tsujii1, Takayuki Ito2, Hiroshi Itokawa2, Koji Matsuo2, Honguh Yoshinori3, Naoki Tamaoki3, Kazunari Ishimaru1, and Hidemi Ishiuchi1 1 SoC Research & Development Center, Semiconductor Company, Toshiba Corporation, 8,Shinsugita-Cho,Isogo-Ku, Yokohama, 235-8522, Japan 2 Process & Manufacturing Engineering Center, Semiconductor Company, Toshiba Corporation, 8,Shinsugita-Cho,Isogo-Ku, Yokohama, 235-8522, Japan 3 Corporate R & D Center, Toshiba Corporation, 1 Komukai Toshiba-cho, Saiwai-ku, Kawasaki, 242-8582, Japan
ABSTRACT We have investigated MSA, namely, Laser Spike Annealing (LSA) and Flash Lamp Annealing (FLA), dopant activation technology of source/drain extension for 45 nm node, which can be substituted for spike RTA. Since it is possible to achieve a similar relation between a sheet resistance and a junction depth by using either FLA or LSA, both annealing methods are capable of providing the junction characteristics required by the ITRS target. However, we have noticed that there are three crucial issues from the viewpoints of device integration and CMOSFET performance: junction leakage current, gate leakage current and pattern dependence. In this paper, we discuss these issues and indicate how to cope with them. INTRODUCTION Ultra shallow junction (USJ) is an essential component for high performance CMOSFETs. However, it has been revealed that it is difficult to achieve the ITRS [1] target for 45 nm node (hp65 nm node) by conventional anneal technologies. Therefore new anneal technologies are required for USJ formation of 45 nm node. Millisecond Anneal (MSA) technology, namely, Laser Spike Annealing (LSA) [2, 3] or Flash Lamp Annealing (FLA) [4, 5], is one of the promising candidates. In this paper, we evaluate the merit both of FLA and LSA technologies, focusing on the process optimization of the 45 nm node CMOSFETs as well as on the above-mentioned process issues. ISSUES AND OPTIMAIZATION OF MILLISECOND ANNEAL PROCESS Junction characteristics Figure 1 shows the relation between the junction depth and the sheet resistance annealed by LSA and FLA, respectively, for n and pMOSFET source/drain extension (SDE). Junction characteristics formed by both types of MSA show a similar tendency.
Sheet resistance (ohm/sq.)
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LSA FLA
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B
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As
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10 15 20 25 30 18 -3 Junction depth (nm) @ 5X10 cm
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10 -3
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B concentration (cm )
-3
As concentration (cm )
Figure 1 Relation of sheet resistance and junction depth for arsenic and boron with LSA and FLA. LSA FLA
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10 15 20 25 30 Depth (nm)
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Figure 2 SIMS profiles of SDE region of (a) n and (b) pMOSFET. Junctions with similar profiles were obtained by using LSA and FLA. Figures 2(a) and (b) show arsenic and boron profiles in the SDE regions annealed by LSA and FLA, res
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