Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET
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ORIGINAL PAPER
Low Frequency Noise Analysis of Single Gate Extended Source Tunnel FET Jagritee Talukdar 1
&
Gopal Rawat 2 & Kunal Singh 3 & Kavicharan Mummaneni 1
Received: 3 July 2020 / Accepted: 12 September 2020 # Springer Nature B.V. 2020
Abstract This paper presents the analysis of noise in Single Gate Extended Source TFET (SG-ESTFET) considering the absence and presence of interface trap charges, when the device is subjected to scaling and variation of parameters like device gate length (Lg), extended source length and height, SiGe mole fraction (x), oxide thickness (tox), gate dielectric material, and frequency (f). Furthermore, the influence of variation of dimensionality and material parameters in presence of noise on Drain Current Noise Power Spectral Density (Sid) and Gate Voltage Electron Noise Power Spectral Density (Svgee) are studied for different trap charge conditions. Assuming Gaussian distribution of trap charges at the interface, it is perceived that the effect of noise is more as compared to the case of absence of trap charges. In reference to other FET devices, present paper reports that, the proposed SGESTFET device under absence of trap charges, illustrates an improved Sid and Svgee value of 1.4 × 10−29 A2/Hz and 5.21 × 10−16 V2/Hz, respectively whereas under the presence of trap charges, Sid and Svgee value are 6.6 × 10−26 A2/Hz and 8.74 × 10−12 V2/Hz, respectively. Moreover, this study also reports that the generation recombination (G-R) noise is mainly prevailing at low and mid-frequencies in presence of trap charges while diffusion noise is prevailing at high-frequencies. Likewise, the flicker noise is observed to be noteworthy at low and medium-frequencies in absence of trap charges. Keywords Trap charges . TFET degradation . SRH . Bandgap narrowing . Fermi-Dirac statistic
1 Introduction The advancement of semiconductor industry and material science has demonstrated excessive importance in most aspects of modern society. MOS transistors are assumed as brick units in ICs and conquer the central position in contemporary electronic devices. Since the introduction of miniaturization concept in 1960s (i.e. Moore’s Law), the integration density has grown-up exponentially, leading to continuous and stringent efforts to comply the goal of increasing performance [1]. To keep footpath with the ITRS roadmap, we have mainly
* Jagritee Talukdar [email protected] 1
Department of Electronics and Communication Engineering, NIT Silchar, Silchar, Assam, India
2
Department of Electronics and Communication Engineering, NIT Hamirpur, Hamirpur, Himachal Pradesh, India
3
Department of Electronics and Communication Engineering, NIT Jamshedpur, Jamshedpur, Jharkhand, India
observed technological revolutions which include scaling of the device dimensions [2], addition of novel materials [3], and modernization in the fabrication process [4]. Undesirably with scaling and other developments, the main difficulty is complex short channel effects (SCEs), which leads to negotiation of long term r
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