Low power balanced balun LNA employing double noise-canceling techniques
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Low power balanced balun LNA employing double noise-canceling techniques Razieh Eskandari1 • Afshin Ebrahimi1
•
Hassan Faraji Baghtash1
Received: 3 December 2019 / Revised: 31 May 2020 / Accepted: 17 July 2020 Ó Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract This paper presents a wideband low power balun LNA with double noise canceling techniques and symmetric outputs. First, the CS amplifier in parallel with the CG stage cancels the noise and distortion of the CG amplifier. Second, an auxiliary amplifier (Aux) is employed in the CS stage to reduces the noise of the CS stage and avoids traditional up scaling of the CS stage. Moreover, the employed Aux stage reduces the output impedance and allows CG and CS stages to drive equal loads. The modified CS stage overcomes the disadvantages of high power consumption and weak output balance in conventional balun LNAs and improves IIP2. Besides, a feedback loop is utilized around the CG amplifier to match the input in a wide frequency band utilizing a low power CG stage. Lower transconductance in the CS stage beside the current reused technique in the CG stage significantly reduces power consumption. The post-layout simulation of the proposed LNA in 180 nm RF CMOS process shows a maximum voltage gain of 20.2 dB with - 3 dB bandwidth of 0.4–2.8 GHz. The minimum NF is 2.65 dB with input matching better than - 12 dB in BW. The third input intercept point (IIP3) is - 0.008 dBm. The consuming power is 4.5 mW from 1.5 V DC supply and the chip area is only 0.038 mm2. Keywords Current reuse Distortion canceling Inductor-less Low noise amplifier Low power Noise cancellation Wideband
1 Introduction Even-order distortion considerably defects the performance of direct-conversion receivers. As the circuits in the receiver chain are traditionally in differential form and provide high IIP2, the LNAs leave as the IIP2 bottleneck in the receiver front-end [1]. Due to the symmetry, differential LNAs present high IIP2’s. Although some random asymmetries deteriorate IIP2, the value is still high. However, differential LNAs require external or integrated balun. The external balun presents low loss but high board area and costs. On-chip balun produces high loss and large capacitances [2]. The balun LNAs, nullify the cost and insertion loss of a balun. The main topology used to implement balun LNA is the common-gate stage in parallel to a common-source stage & Afshin Ebrahimi [email protected] 1
Faculty of Electrical Engineering, Sahand University of Technology, Sahand New Town, Tabriz, Iran
(CG-CS) [3–6]. In this topology, the noise and distortion generated by the CG stage are canceled by the CS stage. To minimize the noise of the CS stage and to avoid gain imbalance, the resistance and transconductance of the CSstage are scaled simultaneously (admittance scaling) [4]. Nevertheless, admittance scaling reduces the output symmetry of the structure. In other words, the imbalance loads and bias currents in the CG and CS branches weaken the output bal
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