Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack
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Low temperature growth and reliability of ferroelectric memory cell integrated on Si with conducting barrier stack A. M. Dhote, S. Madhukar, D. Young, T. Venkatesan,a) and R. Ramesha) Department of Materials and Nuclear Engineering, University of Maryland, College Park, Maryland 20742
C. M. Cotell Surface Modification Branch, U.S. Naval Research Laboratory, Washington, DC 20375
Joseph M. Benedetto Army Research Laboratories, Adelphi, Maryland 20783 (Received 23 April 1996; accepted 5 December 1996)
Polycrystalline LSCO/PNZT/LSCO ferroelectric capacitor heterostructures were grown by pulsed laser deposition using a composite conducting barrier layer of PtyTiN on poly-SiySi substrate. The growth of the ferroelectric heterostructure is accomplished at a temperature in the range of 500 –600 ±C. This integration results in a 3-dimensional stacked capacitor-transistor geometry which is important for high density nonvolatile memory (HDNVM) applications. Transmission electron microscopy shows smooth substrate-film and film-film interfaces without any perceptible interdiffusion. The ferroelectric properties and reliability of these integrated capacitors were studied extensively at room temperature and 100 ±C for different growth temperatures. The capacitors exhibit excellent reliability, both at room temperature and at elevated temperatures, making them very desirable for HDNVM applications.
I. INTRODUCTION
Recently, there has been growing interest in ferroelectric metal oxide thin film capacitors for their potential use in a variety of microelectronic devices, including primarily nonvolatile memory devices. Several programs are on-going with extensive investigation1–10,14 addressing fabrication and application issues of ferroelectric films. Current efforts are strongly focused on the integration of these ferroelectric capacitors with existing silicon-based technology to fabricate transistorcapacitor (1T-1C) based storage elements.3,4,11–16 For ultrahigh memory densities, the one transistor-one capacitor arrangement can be shrunk by building complex 3-dimensional structures to stack them together. Such a high density memory architecture requires the integration of the ferroelectric capacitor stack such that the bottom electrode is in metallic contact with the source or drain of the pass-gate transistor, as illustrated schematically in Fig. 1. Such an integration process requires a conducting barrier layer (or composite barrier stack) that can prevent chemical reaction between the perovskite ferroelectric stack and Si-CMOS. TiN is a promising conducting barrier material that is well accepted by the Si-CMOS industry. It can be grown on a poly-SiySi a)
Present address: Center for Superconductivity Research, Department of Physics, University of Maryland, College Park, Maryland 20742. J. Mater. Res., Vol. 12, No. 6, Jun 1997
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surface with high quality. However, direct growth of oxide ferroelectrics such as LSCO/PNZT/LSCO on
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