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1250-G07-04

Low Temperature Growth of Silicon Structures for Application in Flash Memory Devices Thomas A. Mih, Shashi Paul1, Richard B. M. Cross Emerging Technologies Research Centre, De Montfort University, LE1 9BH Leicester, United Kingdom ABSTRACT An in-depth study of the structural and electrical properties of silicon (Si) films deposited by a novel low temperature technique at temperatures less than 400°C in a 13.56 MHz RF PECVD reactor is reported. The method is based on substrates having to undergo some initial preparatory steps (IPS) before the deposition of Si films in the PECVD chamber. The optical band gap of Si films deposited using this novel technique narrowed to 1.25 eV from 1.78 eV using the traditional a-Si:H deposition recipe. No annealing of any form was performed on the films to attain this band gap. Furthermore, photosensitivities for these films under various deposition conditions were of order 100 compared to 104 for a-Si:H films deposited under like conditions. Using metal-insulator-semiconductor devices, the Si films grown by this novel technique exhibit charge storage and memory behaviour unlike their amorphous counterparts. However, device endurance has been found to be inadequate, probably due to the presence of some contaminants - notably interstitial oxygen - which has been found elsewhere to have adverse effects on the electrical characteristics of Si films. If well harnessed, we suggest Si structures grown by this novel growth technique could be well-suited for flash memory applications, particularly 3-D flash which requires process temperatures to be less than 400 °C.

INTRODUCTION The continuous down-scaling of flash memory cell layers is approaching a dead-end, where leakage currents will increase significantly and impact data retention. This challenge, coupled with the requirements of dielectric quality [1], may result in less integration and performance gains leading to flash performance and reliability being seriously degraded. Threedimensional (3-D) cell architecture is one solution suggested to avert these problems and boost the performance of flash devices [2, 3]. It is attractive as it permits the integration of longretention and high-density cells without compromising device reliability [4]. However, high temperature processing of memory layers is not ideal for 3-D stacked memory architecture, as it stresses device structures - especially at interfaces between different materials. We have developed a novel methodology, which involves an initial substrate preparatory ritual, for growing high-quality silicon (Si) structures at ≤ 400 °C [5]. The advantage of this method compared with solid-phase crystallization (SPC) of a-Si:H is that it by-passes the long hours of annealing necessary for the SPC of a-Si:H. We have previously demonstrated the suitability of this growth technique for future 3-D flash memory technology [6]. In this study, we have used metal-insulator-semiconductor (MIS) devices, which mimic memory devices, to demonstrate the suitability of the low temperature-