Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology
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Material engineering for silicon tunnel field-effect transistors: isoelectronic trap technology Takahiro Mori, Nanoelectronics Research Institute (NeRI), National Institute of Advanced Industrial Science and Technology (AIST), Central 2, 1-1-1 Umezono, Tsukuba, Ibaraki 305-8568, Japan Shota Iizuka†, and Takashi Nakayama, Graduate School of Science, Chiba University, 1-33 Yayoi, Inage, Chiba 263-8522, Japan Address all correspondence to Takahiro Mori at [email protected] (Received 12 June 2017; accepted 26 July 2017)
Abstract The tunnel field-effect transistor (TFET) is one of the candidates replacing conventional metal–oxide–semiconductor field-effect transistors to realize low-power-consumption large-scale integration (LSI). The most significant issue in the practical application of TFETs concerns their low tunneling current. Si is an indirect-gap material having a low band-to-band tunneling probability and is not favored for the channel. However, a new technology to enhance tunneling current in Si-TFETs utilizing the isoelectronic trap (IET) technology was recently proposed. IET technology provides a new approach to realize low-power-consumption LSIs with TFETs. The present paper reviews the state-of-the-art research and future prospects of Si-TFETs with IET technology.
Introduction The performance improvement of large-scale integration (LSI) has progressed owing to the miniaturization of transistors. The degree of integration has increased following Moore’s law, which predicted that the number of components in LSI would doubles every 2 years.[1,2] This prediction has surprisingly come true since—the semiconductor industry has made constant efforts to continue satisfying the law. The increase in the number of transistors has been directly linked to the growth of computing performance, and such continuous improvement of computing performance has been realized over the last 70 years. Koomey et al. examined the strong correlation between computing performance and power efficiency of computation.[3] Their work showed that the improvement of power efficiency is essential for the improvement of computing performance. From the perspective of electronic devices, the improvement of power consumption of transistors paved the way to increase the available number of transistors with a limited power supply, which resulted in the successful improvement of computing performance. In other words, low-power consumption is the essence of transistor miniaturization. This has enabled us to realize outstanding applications such as notebook personal computers, smartphones, tablets, and so on. Dennard scaling guided the miniaturization of metal–oxide– semiconductor field-effect transistors (MOSFETs), which are † Present address: Center for Green Research on Energy and Environmental Materials (GREEN), National Institute for Materials Science (NIMS), 1-1 Namiki, Tsukuba, Ibaraki 305-0044, Japan.
the building blocks of contemporary LSIs.[4] Dennard scaling provides guidelines to reduce the power consumption of MOSFETs
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