A Totally Wet Etch Fabrication Technology for Amorphous Silicon Thin Film Transistors
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AMIR MASOUD MIRI AND SAVVAS G. CHAMBERLAIN University of Waterloo, Department of Electrical and Computer Engineering, Waterloo, Ontario Canada N2L 3G1.
ABSTRACT We developed a totally wet etch processing technology for the fabrication of inverted staggered amorphous silicon thin-film transistors (TFTs) and circuits. In this technology we take advantage of highly etch selective KOH and BF base solutions for amorphous silicon and silicon nitride layers. Our technology is simple, reproducible, fully compatible with positive photo-resist lithography techniques, and suitable for mass production of amorphous silicon TFT based circuits. Using this process, we fabricated thin film 2 transistors which have an effective mobility of 0.83 cm V-I ยง1 , threeshold voltage of 2V and on/off current ratio of 107. In this paper we discuss the details of our fabrication process and report on the chemical conditions of the etching and deposition processes.
INTRODUCTION The rapidly growing market [1,21 and application area for amorphous silicon thin-film transistor based circuits demand the development of a low cost, high performance fabrication process for these transistors and corresponding circuits. Unlike crystalline silicon technology, for which a fabrication process is well defined, there is no well-defined standard fabrication process for a-Si:H TFTs. An optimum process is yet to be defined. In patterning a-Si:H TFTs a simple, reproducible and cheap technique is desired. For best device performance, such a technique should avoid damage to the a-Si:H and silicon nitride and their interface. So far, conventional plasma dry etch (or reactive ion etching, RIE) methods have been extensively used in the fabrication of amorphous silicon TFTs [3]. Although, RIE methods are environmentally cleaner and give a better control over small geometry designs, they have some serious draw backs. Dry etching causes surface damage and bulk damage. Surface damage is mainly caused by ion bombardment. Bulk damage is caused by the plasma radiation, e.g., UV and other high energy photons. The adverse effects of these damages on the TFT characteristics include a high threshold voltage, a high off current, and the divergence of the transfer characteristic curves under different drain voltages [4]. These damages can only be repaired by long thermal annealing steps [4]. To avoid such damages to the TFT's films and/or interfaces a wet etching method is desired rather than plasma etching. The demand for mass production of large area a-Si:H TFT based circuits also suggests a wet etching method. Also, a wet etch method usually yields more uniform etching especially for large areas. We developed a totally wet etch fabrication process technology to remedy the drawbacks of the dry etch method. We also designed our TFT wet etch process steps such that we can integrate other common a-Si:H circuit components on the same substrate without adding to the complexity of the process. The challenge in designing a wet etch method is to find selective and controllable etchant
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