Material Reliability and Integration Issues of Polyimide and Benzocyclobutene Interlayer Dielectric Materials
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Material Reliability and Integration Issues of Polyimide and Benzocyclobutene Interlayer Dielectric Materials Parshuram B. Zantye1, Ashok Kumar1, R. Gopalkrishnan2 and S. Balakumar2 1 Department of Mechanical Engineering, Nanomaterials & Nanomanufacturing Research Center, University of South Florida, Tampa, Florida-33620 2 Institute of Microelectronics, Science Park II, Singapore, 117685 ABSTRACT The constant push for decreasing the Resistance-Capacitance (RC) delay has led to the implementation of Multilevel Metallization (MLM) scheme for interconnect wiring, Cu as the wiring material and low κ materials as Interlayer Dielectric (ILD). Polymeric materials are being explored to replace SiO2 based ILD materials in the next generation ICs. Several reliability and integration challenges arise during integration of the candidate polymeric ILD when they are subjected to planarization by Chemical Mechanical Polishing (CMP). In this research, we have performed a comparative study of certain candidate low κ materials: 1) undoped SiO2 (standard), 2) Polyimide and 3) Benzocyclobutene (BCB). We have studied the impact of reduction in dielectric constant on the mechanical and tribological properties, and the CMP performance of these ILD materials. The adverse effect of shear and mechanical abrasion due to decreased mechanical properties of the low κ materials induced numerous defects during CMP. INTRODUCTION The RC delay in the IC operation is directly proportional to: 1) resistivity of the wiring materials, 2) dielectric constant of the ILD, and 3) length of the interconnect line; and is inversely proportional to interconnect wiring pitch and thickness1, 2. To decrease the RC delay: 1) Cu has replaced Al as interconnect wiring materials due to its lower resistivity, 2) several novel low κ materials are being explored, and 3) multilevel metallization scheme of wiring is being implemented. Chemical Mechanical Planarization (CMP) is the process of choice to planarize the constituent materials of IC interconnects scheme1. Though there is a general consensus in implementing Cu in IC interconnect wiring, several different materials are currently being explored as candidate ILD. The different materials currently under investigation to replace SiO2 can be broadly classified as: 1) Doped (e.g. Carbon, Fluorine, Chlorine doped silica), 2) polymeric (SiLKTM, BCB, Polyimide etc.), 3) Porous (ceramic or polymeric) materials3. An ideal dielectric material should have: 1) high mechanical strength, 2) good dimensional stability, 3) high thermal stability, 4) ease of pattern and etch of sub-micrometer features, 5) low moisture absorption and permeation, 6) good adhesion, 7) low stress, 8) good etch selectivity to metal, 9) high thermal conductivity, 10) good gap filling and planarization capability3. Due to the known weak mechanical integrity and interfacial fracture toughness of the porous, doped and polymeric materials, the reliability and integration challenges associated with these materials are being extensively investigated befo
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