Model and Design of Improved Current Mode Logic Gates Differential a
This book presents MOSFET-based current mode logic (CML) topologies, which increase the speed, and lower the transistor count, supply voltage and power consumption. The improved topologies modify the conventional PDN, load, and the current source sections
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Model and Design of Improved Current Mode Logic Gates Differential and Single-ended
Model and Design of Improved Current Mode Logic Gates
Kirti Gupta Neeta Pandey Maneesha Gupta •
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Model and Design of Improved Current Mode Logic Gates Differential and Single-ended
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Kirti Gupta Department of Electronics and Communication Bharati Vidyapeeth’s College of Engineering New Delhi, Delhi, India
Neeta Pandey Department of Electronics and Communication Delhi Technological University New Delhi, Delhi, India
Maneesha Gupta Department of Electronics and Communication Netaji Subhas University of Technology Dwarka, Delhi, India
ISBN 978-981-15-0981-0 ISBN 978-981-15-0982-7 https://doi.org/10.1007/978-981-15-0982-7
(eBook)
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Preface
Technological evolution has facilitated the coexistence of digital and analog circuits on a single chip. A single-chip realization has a profound impact on performance, cost, and size. Such chip eases signal acquisition which falls primarily in analog domain and signal processing that is predominately done in the digital domain. The digital circuit design revolves around CMOS due to negligible static power, but it consumes dynamic power which becomes severe at high frequencies and also results in large current spikes during switching event (switching noise). As a consequence, the resolution of analog circuits may decrease; therefore, this issue needs special attention. Alternate logic styles are explored to reduce switching noise which work on keeping power supply current nearly constant during the switching event and/or working with smaller volta
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