Modeling and simulation of a dual-material asymmetric heterodielectric-gate TFET
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Modeling and simulation of a dual‑material asymmetric heterodielectric‑gate TFET I. Vivek Anand1 · T. S. Arun Samuel1 · P. Vimala2 Received: 24 April 2020 / Accepted: 28 July 2020 © Springer Science+Business Media, LLC, part of Springer Nature 2020
Abstract Analytical modeling of a dual-material asymmetric heterodielectric-gate tunnel field-effect transistor (FET) is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different work functions is used to eliminate the influence of the OFF-current (leakage current) and short-channel effects in the device. The lengths of metal 1 and metal 2 are taken to be 10 nm and 10 nm, respectively, and the device performance is analyzed. Expressions for the surface potential, electric field, and drain current are obtained by using a two-dimensional (2D) mathematical model, whose results are compared with those obtained using the Silvaco technology computer-aided design (TCAD) simulator, revealing good agreement. The proposed dual-material asymmetric gate tunnel FET produces an improved ON-current of 10−5 A/µm and a decreased OFF current of 10−10 A/µm, with an ON/OFF ratio of 105. Keywords Asymmetric gate · Leakage current · Band-to-band tunneling · ON current
1 Introduction Impressive developments in semiconductor devices have been achieved by scaling the dimensions of complementary metal–oxide–semiconductor (CMOS) technology without altering its electrical properties. The enhanced performance of such devices is obtained by reducing the feature size. However, conventional MOS transistors suffer from high power dissipation and leakage current. Meanwhile, threshold voltage roll-off, drain-induced barrier lowering, and higher OFF-state current (IOFF) are other undesirable effects observed in metal–oxide–semiconductor field-effect transistors (MOSFETs). Moreover, at room temperature, the subthreshold swing of MOS transistors is limited to 60 mV/decade [1–3]. Several multigate structures have been * T. S. Arun Samuel [email protected] I. Vivek Anand [email protected] P. Vimala [email protected] 1
Department of ECE, National Engineering College, Kovilpatti, India
Department of ECE, Dayananda Sagar College of Engineering, Bengaluru, India
2
proposed to eliminate the influence of such short-channel effects and leakage currents in the device. The fascinating physical and electrical properties of tunnel FETs using an asymmetric gate have received significant attention from the semiconductor community, representing a promising candidate to eliminate the drawbacks of MOSFETs and improve the ON-current [4–8]. Tunneling FET devices are suited for ultralow-power applications. Asymmetric gate tunnel FETs reduce the effect of ambipolar current conduction. The device considered herein is constructed with two oxide layers formed of hafnium oxide and S iO2, resulting in an asymmetric structure. The bandgap at the source and channel interface are reduced to increase the ON-current and reduce the
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