3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces
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1112-E02-01
3D Integration Using Adhesive, Metal, and Metal/Adhesive as Wafer Bonding Interfaces Jian-Qiang Lu1, J. Jay McMahon1,2 and Ronald J. Gutmann1,3 1
Department of Electrical, Computer, and Systems Engineering; Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, NY 12180. [email protected] 2 Current affiliation: GE Global Research Center, Niskayuna, NY 12309 3 Consultant and Professor Emeritus at Rensselaer Polytechnic Institute, Troy, NY 12180 ABSTRACT Three-dimensional (3D) integration is an emerging technology that vertically stacks and interconnects multiple materials, technologies and functional components to form highly integrated micro/nano-systems. This paper reviews the materials and technologies for three wafer bonding approaches to 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces. Similarities and differences in architectural advantages and technology challenges are presented, with recent research advances discussed. INTRODUCTION Three-dimensional (3D) hyper-integration* is an emerging technology that can form highly integrated systems by vertically stacking and connecting various materials, technologies, and functional components together [1, 2]. Figure 1 shows schematic representations of major 3D integration approaches pursued currently [1]. They can be divided into three categories based on their similarity to other technologies: • 3D packaging technology (Fig. 1a-c); • Transistor build-up 3D technology (Fig. 1d-f); • Wafer-level, back-end-of-the-line (BEOL)-compatible 3D technology (Fig. 1g-k). The potential benefits of 3D integration varies for each approach; they include multifunctionality, small form factor, increased speed and data bandwidth, reduced power, reduced component packaging, increased yield and reliability, flexible heterogeneous integration, and reduced overall costs. For example, a small form factor is achieved by stacking active component layers on top of one another in any 3D approach. Since classical CMOS device scaling has stalled, this third dimension would allow extending Moore’s law to ever higher density, higher functionality, and higher performance, while more diversified materials and devices can be integrated with lower cost. It could be expected that the industry paradigm will shift to a new era of 3D integration that will offer tremendous global opportunities for highly integrated systems. This paper provides a review of the materials and technologies for three wafer bonding approaches to monolithic, wafer-level, BEOL-compatible 3D integration using adhesive, metal, and metal/adhesive as the bonding interfaces [3-22]. Similarities and differences in architectural advantages and technology challenges are presented. Recent research advances and potential reliability issues are discussed. Other 3D approaches beyond the scope of this manuscript are covered elsewhere [1]. *
The term ‘hyper-integration’ means to integrate various materials, processing technologies, and functions beyond ultra-large scale integration
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